blob: 5a466e1d5dab8306fcc82126a09bd865bb7cd598 [file] [log] [blame]
Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Aart Bikc7782262017-01-13 16:20:08 -0800353void X86Assembler::movaps(XmmRegister dst, const Address& src) {
354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0x0F);
356 EmitUint8(0x28);
357 EmitOperand(dst, src);
358}
359
360
361void X86Assembler::movups(XmmRegister dst, const Address& src) {
362 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363 EmitUint8(0x0F);
364 EmitUint8(0x10);
365 EmitOperand(dst, src);
366}
367
368
369void X86Assembler::movaps(const Address& dst, XmmRegister src) {
370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
371 EmitUint8(0x0F);
372 EmitUint8(0x29);
373 EmitOperand(src, dst);
374}
375
376
377void X86Assembler::movups(const Address& dst, XmmRegister src) {
378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
379 EmitUint8(0x0F);
380 EmitUint8(0x11);
381 EmitOperand(src, dst);
382}
383
384
Ian Rogers2c8f6532011-09-02 17:16:34 -0700385void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
387 EmitUint8(0xF3);
388 EmitUint8(0x0F);
389 EmitUint8(0x10);
390 EmitOperand(dst, src);
391}
392
393
Ian Rogers2c8f6532011-09-02 17:16:34 -0700394void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
396 EmitUint8(0xF3);
397 EmitUint8(0x0F);
398 EmitUint8(0x11);
399 EmitOperand(src, dst);
400}
401
402
Ian Rogers2c8f6532011-09-02 17:16:34 -0700403void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700404 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
405 EmitUint8(0xF3);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitXmmRegisterOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0x66);
415 EmitUint8(0x0F);
416 EmitUint8(0x6E);
417 EmitOperand(dst, Operand(src));
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0x66);
424 EmitUint8(0x0F);
425 EmitUint8(0x7E);
426 EmitOperand(src, Operand(dst));
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x58);
435 EmitXmmRegisterOperand(dst, src);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0xF3);
442 EmitUint8(0x0F);
443 EmitUint8(0x58);
444 EmitOperand(dst, src);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0xF3);
451 EmitUint8(0x0F);
452 EmitUint8(0x5C);
453 EmitXmmRegisterOperand(dst, src);
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x5C);
462 EmitOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x59);
471 EmitXmmRegisterOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x59);
480 EmitOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5E);
489 EmitXmmRegisterOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x5E);
498 EmitOperand(dst, src);
499}
500
501
Aart Bikc7782262017-01-13 16:20:08 -0800502void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0x0F);
505 EmitUint8(0x58);
506 EmitXmmRegisterOperand(dst, src);
507}
508
509
510void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
512 EmitUint8(0x0F);
513 EmitUint8(0x5C);
514 EmitXmmRegisterOperand(dst, src);
515}
516
517
518void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x0F);
521 EmitUint8(0x59);
522 EmitXmmRegisterOperand(dst, src);
523}
524
525
526void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528 EmitUint8(0x0F);
529 EmitUint8(0x5E);
530 EmitXmmRegisterOperand(dst, src);
531}
532
533
534void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
536 EmitUint8(0x66);
537 EmitUint8(0x0F);
538 EmitUint8(0x28);
539 EmitXmmRegisterOperand(dst, src);
540}
541
542
543void X86Assembler::movapd(XmmRegister dst, const Address& src) {
544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
545 EmitUint8(0x66);
546 EmitUint8(0x0F);
547 EmitUint8(0x28);
548 EmitOperand(dst, src);
549}
550
551
552void X86Assembler::movupd(XmmRegister dst, const Address& src) {
553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
554 EmitUint8(0x66);
555 EmitUint8(0x0F);
556 EmitUint8(0x10);
557 EmitOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(const Address& dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x29);
566 EmitOperand(src, dst);
567}
568
569
570void X86Assembler::movupd(const Address& dst, XmmRegister src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x11);
575 EmitOperand(src, dst);
576}
577
578
Ian Rogers2c8f6532011-09-02 17:16:34 -0700579void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0xD9);
582 EmitOperand(0, src);
583}
584
585
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500586void X86Assembler::fsts(const Address& dst) {
587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588 EmitUint8(0xD9);
589 EmitOperand(2, dst);
590}
591
592
Ian Rogers2c8f6532011-09-02 17:16:34 -0700593void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
595 EmitUint8(0xD9);
596 EmitOperand(3, dst);
597}
598
599
Ian Rogers2c8f6532011-09-02 17:16:34 -0700600void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF2);
603 EmitUint8(0x0F);
604 EmitUint8(0x10);
605 EmitOperand(dst, src);
606}
607
608
Ian Rogers2c8f6532011-09-02 17:16:34 -0700609void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0xF2);
612 EmitUint8(0x0F);
613 EmitUint8(0x11);
614 EmitOperand(src, dst);
615}
616
617
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0xF2);
621 EmitUint8(0x0F);
622 EmitUint8(0x11);
623 EmitXmmRegisterOperand(src, dst);
624}
625
626
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000627void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0x66);
630 EmitUint8(0x0F);
631 EmitUint8(0x16);
632 EmitOperand(dst, src);
633}
634
635
636void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0x66);
639 EmitUint8(0x0F);
640 EmitUint8(0x17);
641 EmitOperand(src, dst);
642}
643
644
645void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
646 DCHECK(shift_count.is_uint8());
647
648 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
649 EmitUint8(0x66);
650 EmitUint8(0x0F);
651 EmitUint8(0x73);
652 EmitXmmRegisterOperand(3, reg);
653 EmitUint8(shift_count.value());
654}
655
656
Calin Juravle52c48962014-12-16 17:02:57 +0000657void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
658 DCHECK(shift_count.is_uint8());
659
660 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
661 EmitUint8(0x66);
662 EmitUint8(0x0F);
663 EmitUint8(0x73);
664 EmitXmmRegisterOperand(2, reg);
665 EmitUint8(shift_count.value());
666}
667
668
669void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
670 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
671 EmitUint8(0x66);
672 EmitUint8(0x0F);
673 EmitUint8(0x62);
674 EmitXmmRegisterOperand(dst, src);
675}
676
677
Ian Rogers2c8f6532011-09-02 17:16:34 -0700678void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700679 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
680 EmitUint8(0xF2);
681 EmitUint8(0x0F);
682 EmitUint8(0x58);
683 EmitXmmRegisterOperand(dst, src);
684}
685
686
Ian Rogers2c8f6532011-09-02 17:16:34 -0700687void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700688 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
689 EmitUint8(0xF2);
690 EmitUint8(0x0F);
691 EmitUint8(0x58);
692 EmitOperand(dst, src);
693}
694
695
Ian Rogers2c8f6532011-09-02 17:16:34 -0700696void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700697 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
698 EmitUint8(0xF2);
699 EmitUint8(0x0F);
700 EmitUint8(0x5C);
701 EmitXmmRegisterOperand(dst, src);
702}
703
704
Ian Rogers2c8f6532011-09-02 17:16:34 -0700705void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700706 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
707 EmitUint8(0xF2);
708 EmitUint8(0x0F);
709 EmitUint8(0x5C);
710 EmitOperand(dst, src);
711}
712
713
Ian Rogers2c8f6532011-09-02 17:16:34 -0700714void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
716 EmitUint8(0xF2);
717 EmitUint8(0x0F);
718 EmitUint8(0x59);
719 EmitXmmRegisterOperand(dst, src);
720}
721
722
Ian Rogers2c8f6532011-09-02 17:16:34 -0700723void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700724 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
725 EmitUint8(0xF2);
726 EmitUint8(0x0F);
727 EmitUint8(0x59);
728 EmitOperand(dst, src);
729}
730
731
Ian Rogers2c8f6532011-09-02 17:16:34 -0700732void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700733 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
734 EmitUint8(0xF2);
735 EmitUint8(0x0F);
736 EmitUint8(0x5E);
737 EmitXmmRegisterOperand(dst, src);
738}
739
740
Ian Rogers2c8f6532011-09-02 17:16:34 -0700741void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
743 EmitUint8(0xF2);
744 EmitUint8(0x0F);
745 EmitUint8(0x5E);
746 EmitOperand(dst, src);
747}
748
749
Aart Bikc7782262017-01-13 16:20:08 -0800750void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
751 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
752 EmitUint8(0x66);
753 EmitUint8(0x0F);
754 EmitUint8(0x58);
755 EmitXmmRegisterOperand(dst, src);
756}
757
758
759void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
760 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
761 EmitUint8(0x66);
762 EmitUint8(0x0F);
763 EmitUint8(0x5C);
764 EmitXmmRegisterOperand(dst, src);
765}
766
767
768void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
769 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
770 EmitUint8(0x66);
771 EmitUint8(0x0F);
772 EmitUint8(0x59);
773 EmitXmmRegisterOperand(dst, src);
774}
775
776
777void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
778 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
779 EmitUint8(0x66);
780 EmitUint8(0x0F);
781 EmitUint8(0x5E);
782 EmitXmmRegisterOperand(dst, src);
783}
784
785
Aart Bik68555e92017-02-13 14:28:45 -0800786void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
787 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
788 EmitUint8(0x66);
789 EmitUint8(0x0F);
790 EmitUint8(0x6F);
791 EmitXmmRegisterOperand(dst, src);
792}
793
794
795void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
796 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
797 EmitUint8(0x66);
798 EmitUint8(0x0F);
799 EmitUint8(0x6F);
800 EmitOperand(dst, src);
801}
802
803
804void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
805 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
806 EmitUint8(0xF3);
807 EmitUint8(0x0F);
808 EmitUint8(0x6F);
809 EmitOperand(dst, src);
810}
811
812
813void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
814 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
815 EmitUint8(0x66);
816 EmitUint8(0x0F);
817 EmitUint8(0x7F);
818 EmitOperand(src, dst);
819}
820
821
822void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
823 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
824 EmitUint8(0xF3);
825 EmitUint8(0x0F);
826 EmitUint8(0x7F);
827 EmitOperand(src, dst);
828}
829
830
831void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
832 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
833 EmitUint8(0x66);
834 EmitUint8(0x0F);
835 EmitUint8(0xFE);
836 EmitXmmRegisterOperand(dst, src);
837}
838
839
840void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
841 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
842 EmitUint8(0x66);
843 EmitUint8(0x0F);
844 EmitUint8(0xFA);
845 EmitXmmRegisterOperand(dst, src);
846}
847
848
849void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
850 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
851 EmitUint8(0x66);
852 EmitUint8(0x0F);
853 EmitUint8(0x38);
854 EmitUint8(0x40);
855 EmitXmmRegisterOperand(dst, src);
856}
857
858
Ian Rogers2c8f6532011-09-02 17:16:34 -0700859void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700860 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
861 EmitUint8(0xF3);
862 EmitUint8(0x0F);
863 EmitUint8(0x2A);
864 EmitOperand(dst, Operand(src));
865}
866
867
Ian Rogers2c8f6532011-09-02 17:16:34 -0700868void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700869 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
870 EmitUint8(0xF2);
871 EmitUint8(0x0F);
872 EmitUint8(0x2A);
873 EmitOperand(dst, Operand(src));
874}
875
876
Ian Rogers2c8f6532011-09-02 17:16:34 -0700877void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700878 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
879 EmitUint8(0xF3);
880 EmitUint8(0x0F);
881 EmitUint8(0x2D);
882 EmitXmmRegisterOperand(dst, src);
883}
884
885
Ian Rogers2c8f6532011-09-02 17:16:34 -0700886void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700887 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
888 EmitUint8(0xF3);
889 EmitUint8(0x0F);
890 EmitUint8(0x5A);
891 EmitXmmRegisterOperand(dst, src);
892}
893
894
Ian Rogers2c8f6532011-09-02 17:16:34 -0700895void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700896 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
897 EmitUint8(0xF2);
898 EmitUint8(0x0F);
899 EmitUint8(0x2D);
900 EmitXmmRegisterOperand(dst, src);
901}
902
903
Ian Rogers2c8f6532011-09-02 17:16:34 -0700904void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700905 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
906 EmitUint8(0xF3);
907 EmitUint8(0x0F);
908 EmitUint8(0x2C);
909 EmitXmmRegisterOperand(dst, src);
910}
911
912
Ian Rogers2c8f6532011-09-02 17:16:34 -0700913void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700914 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
915 EmitUint8(0xF2);
916 EmitUint8(0x0F);
917 EmitUint8(0x2C);
918 EmitXmmRegisterOperand(dst, src);
919}
920
921
Ian Rogers2c8f6532011-09-02 17:16:34 -0700922void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700923 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
924 EmitUint8(0xF2);
925 EmitUint8(0x0F);
926 EmitUint8(0x5A);
927 EmitXmmRegisterOperand(dst, src);
928}
929
930
Ian Rogers2c8f6532011-09-02 17:16:34 -0700931void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700932 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
933 EmitUint8(0xF3);
934 EmitUint8(0x0F);
935 EmitUint8(0xE6);
936 EmitXmmRegisterOperand(dst, src);
937}
938
939
Ian Rogers2c8f6532011-09-02 17:16:34 -0700940void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700941 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
942 EmitUint8(0x0F);
943 EmitUint8(0x2F);
944 EmitXmmRegisterOperand(a, b);
945}
946
947
Aart Bik18ba1212016-08-01 14:11:20 -0700948void X86Assembler::comiss(XmmRegister a, const Address& b) {
949 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
950 EmitUint8(0x0F);
951 EmitUint8(0x2F);
952 EmitOperand(a, b);
953}
954
955
Ian Rogers2c8f6532011-09-02 17:16:34 -0700956void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700957 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
958 EmitUint8(0x66);
959 EmitUint8(0x0F);
960 EmitUint8(0x2F);
961 EmitXmmRegisterOperand(a, b);
962}
963
964
Aart Bik18ba1212016-08-01 14:11:20 -0700965void X86Assembler::comisd(XmmRegister a, const Address& b) {
966 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
967 EmitUint8(0x66);
968 EmitUint8(0x0F);
969 EmitUint8(0x2F);
970 EmitOperand(a, b);
971}
972
973
Calin Juravleddb7df22014-11-25 20:56:51 +0000974void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
975 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
976 EmitUint8(0x0F);
977 EmitUint8(0x2E);
978 EmitXmmRegisterOperand(a, b);
979}
980
981
Mark Mendell9f51f262015-10-30 09:21:37 -0400982void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
983 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
984 EmitUint8(0x0F);
985 EmitUint8(0x2E);
986 EmitOperand(a, b);
987}
988
989
Calin Juravleddb7df22014-11-25 20:56:51 +0000990void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
991 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
992 EmitUint8(0x66);
993 EmitUint8(0x0F);
994 EmitUint8(0x2E);
995 EmitXmmRegisterOperand(a, b);
996}
997
998
Mark Mendell9f51f262015-10-30 09:21:37 -0400999void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1000 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1001 EmitUint8(0x66);
1002 EmitUint8(0x0F);
1003 EmitUint8(0x2E);
1004 EmitOperand(a, b);
1005}
1006
1007
Mark Mendellfb8d2792015-03-31 22:16:59 -04001008void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1009 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1010 EmitUint8(0x66);
1011 EmitUint8(0x0F);
1012 EmitUint8(0x3A);
1013 EmitUint8(0x0B);
1014 EmitXmmRegisterOperand(dst, src);
1015 EmitUint8(imm.value());
1016}
1017
1018
1019void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1020 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1021 EmitUint8(0x66);
1022 EmitUint8(0x0F);
1023 EmitUint8(0x3A);
1024 EmitUint8(0x0A);
1025 EmitXmmRegisterOperand(dst, src);
1026 EmitUint8(imm.value());
1027}
1028
1029
Ian Rogers2c8f6532011-09-02 17:16:34 -07001030void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001031 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1032 EmitUint8(0xF2);
1033 EmitUint8(0x0F);
1034 EmitUint8(0x51);
1035 EmitXmmRegisterOperand(dst, src);
1036}
1037
1038
Ian Rogers2c8f6532011-09-02 17:16:34 -07001039void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001040 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1041 EmitUint8(0xF3);
1042 EmitUint8(0x0F);
1043 EmitUint8(0x51);
1044 EmitXmmRegisterOperand(dst, src);
1045}
1046
1047
Ian Rogers2c8f6532011-09-02 17:16:34 -07001048void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001049 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1050 EmitUint8(0x66);
1051 EmitUint8(0x0F);
1052 EmitUint8(0x57);
1053 EmitOperand(dst, src);
1054}
1055
1056
Ian Rogers2c8f6532011-09-02 17:16:34 -07001057void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001058 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1059 EmitUint8(0x66);
1060 EmitUint8(0x0F);
1061 EmitUint8(0x57);
1062 EmitXmmRegisterOperand(dst, src);
1063}
1064
1065
Aart Bik68555e92017-02-13 14:28:45 -08001066void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001067 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1068 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001069 EmitUint8(0x57);
1070 EmitOperand(dst, src);
1071}
1072
1073
1074void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1076 EmitUint8(0x0F);
1077 EmitUint8(0x57);
1078 EmitXmmRegisterOperand(dst, src);
1079}
1080
1081
1082void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1083 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1084 EmitUint8(0x66);
1085 EmitUint8(0x0F);
1086 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001087 EmitXmmRegisterOperand(dst, src);
1088}
1089
1090
1091void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1092 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1093 EmitUint8(0x66);
1094 EmitUint8(0x0F);
1095 EmitUint8(0x54);
1096 EmitXmmRegisterOperand(dst, src);
1097}
1098
1099
Aart Bik68555e92017-02-13 14:28:45 -08001100void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001101 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1102 EmitUint8(0x66);
1103 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001104 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001105 EmitOperand(dst, src);
1106}
1107
1108
Aart Bik68555e92017-02-13 14:28:45 -08001109void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001110 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1111 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001112 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001113 EmitXmmRegisterOperand(dst, src);
1114}
1115
1116
Mark Mendell09ed1a32015-03-25 08:30:06 -04001117void X86Assembler::andps(XmmRegister dst, const Address& src) {
1118 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1119 EmitUint8(0x0F);
1120 EmitUint8(0x54);
1121 EmitOperand(dst, src);
1122}
1123
1124
Aart Bik68555e92017-02-13 14:28:45 -08001125void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001126 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1127 EmitUint8(0x66);
1128 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001129 EmitUint8(0xDB);
1130 EmitXmmRegisterOperand(dst, src);
1131}
1132
1133
1134void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1136 EmitUint8(0x66);
1137 EmitUint8(0x0F);
1138 EmitUint8(0x56);
1139 EmitXmmRegisterOperand(dst, src);
1140}
1141
1142
1143void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1144 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1145 EmitUint8(0x0F);
1146 EmitUint8(0x56);
1147 EmitXmmRegisterOperand(dst, src);
1148}
1149
1150
1151void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1152 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1153 EmitUint8(0x66);
1154 EmitUint8(0x0F);
1155 EmitUint8(0xEB);
1156 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001157}
1158
1159
Aart Bik12e06ed2017-01-31 16:11:24 -08001160void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1161 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1162 EmitUint8(0x66);
1163 EmitUint8(0x0F);
1164 EmitUint8(0xC6);
1165 EmitXmmRegisterOperand(dst, src);
1166 EmitUint8(imm.value());
1167}
1168
1169
1170void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1171 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1172 EmitUint8(0x0F);
1173 EmitUint8(0xC6);
1174 EmitXmmRegisterOperand(dst, src);
1175 EmitUint8(imm.value());
1176}
1177
1178
Aart Bik68555e92017-02-13 14:28:45 -08001179void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1180 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1181 EmitUint8(0x66);
1182 EmitUint8(0x0F);
1183 EmitUint8(0x70);
1184 EmitXmmRegisterOperand(dst, src);
1185 EmitUint8(imm.value());
1186}
1187
1188
Ian Rogers2c8f6532011-09-02 17:16:34 -07001189void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1191 EmitUint8(0xDD);
1192 EmitOperand(0, src);
1193}
1194
1195
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001196void X86Assembler::fstl(const Address& dst) {
1197 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1198 EmitUint8(0xDD);
1199 EmitOperand(2, dst);
1200}
1201
1202
Ian Rogers2c8f6532011-09-02 17:16:34 -07001203void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001204 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1205 EmitUint8(0xDD);
1206 EmitOperand(3, dst);
1207}
1208
1209
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001210void X86Assembler::fstsw() {
1211 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1212 EmitUint8(0x9B);
1213 EmitUint8(0xDF);
1214 EmitUint8(0xE0);
1215}
1216
1217
Ian Rogers2c8f6532011-09-02 17:16:34 -07001218void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001219 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1220 EmitUint8(0xD9);
1221 EmitOperand(7, dst);
1222}
1223
1224
Ian Rogers2c8f6532011-09-02 17:16:34 -07001225void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001226 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1227 EmitUint8(0xD9);
1228 EmitOperand(5, src);
1229}
1230
1231
Ian Rogers2c8f6532011-09-02 17:16:34 -07001232void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001233 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1234 EmitUint8(0xDF);
1235 EmitOperand(7, dst);
1236}
1237
1238
Ian Rogers2c8f6532011-09-02 17:16:34 -07001239void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001240 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1241 EmitUint8(0xDB);
1242 EmitOperand(3, dst);
1243}
1244
1245
Ian Rogers2c8f6532011-09-02 17:16:34 -07001246void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001247 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1248 EmitUint8(0xDF);
1249 EmitOperand(5, src);
1250}
1251
1252
Roland Levillain0a186012015-04-13 17:00:20 +01001253void X86Assembler::filds(const Address& src) {
1254 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1255 EmitUint8(0xDB);
1256 EmitOperand(0, src);
1257}
1258
1259
Ian Rogers2c8f6532011-09-02 17:16:34 -07001260void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001261 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262 EmitUint8(0xD9);
1263 EmitUint8(0xF7);
1264}
1265
1266
Ian Rogers2c8f6532011-09-02 17:16:34 -07001267void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001268 CHECK_LT(index.value(), 7);
1269 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1270 EmitUint8(0xDD);
1271 EmitUint8(0xC0 + index.value());
1272}
1273
1274
Ian Rogers2c8f6532011-09-02 17:16:34 -07001275void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001276 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1277 EmitUint8(0xD9);
1278 EmitUint8(0xFE);
1279}
1280
1281
Ian Rogers2c8f6532011-09-02 17:16:34 -07001282void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1284 EmitUint8(0xD9);
1285 EmitUint8(0xFF);
1286}
1287
1288
Ian Rogers2c8f6532011-09-02 17:16:34 -07001289void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001290 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1291 EmitUint8(0xD9);
1292 EmitUint8(0xF2);
1293}
1294
1295
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001296void X86Assembler::fucompp() {
1297 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1298 EmitUint8(0xDA);
1299 EmitUint8(0xE9);
1300}
1301
1302
1303void X86Assembler::fprem() {
1304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1305 EmitUint8(0xD9);
1306 EmitUint8(0xF8);
1307}
1308
1309
Ian Rogers2c8f6532011-09-02 17:16:34 -07001310void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001311 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1312 EmitUint8(0x87);
1313 EmitRegisterOperand(dst, src);
1314}
1315
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001316
Ian Rogers7caad772012-03-30 01:07:54 -07001317void X86Assembler::xchgl(Register reg, const Address& address) {
1318 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1319 EmitUint8(0x87);
1320 EmitOperand(reg, address);
1321}
1322
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001323
Serguei Katkov3b625932016-05-06 10:24:17 +06001324void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1325 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1326 EmitUint8(0x80);
1327 EmitOperand(7, address);
1328 EmitUint8(imm.value() & 0xFF);
1329}
1330
1331
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001332void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1333 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1334 EmitUint8(0x66);
1335 EmitComplex(7, address, imm);
1336}
1337
1338
Ian Rogers2c8f6532011-09-02 17:16:34 -07001339void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001340 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1341 EmitComplex(7, Operand(reg), imm);
1342}
1343
1344
Ian Rogers2c8f6532011-09-02 17:16:34 -07001345void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1347 EmitUint8(0x3B);
1348 EmitOperand(reg0, Operand(reg1));
1349}
1350
1351
Ian Rogers2c8f6532011-09-02 17:16:34 -07001352void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001353 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1354 EmitUint8(0x3B);
1355 EmitOperand(reg, address);
1356}
1357
1358
Ian Rogers2c8f6532011-09-02 17:16:34 -07001359void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001360 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1361 EmitUint8(0x03);
1362 EmitRegisterOperand(dst, src);
1363}
1364
1365
Ian Rogers2c8f6532011-09-02 17:16:34 -07001366void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001367 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1368 EmitUint8(0x03);
1369 EmitOperand(reg, address);
1370}
1371
1372
Ian Rogers2c8f6532011-09-02 17:16:34 -07001373void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001374 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1375 EmitUint8(0x39);
1376 EmitOperand(reg, address);
1377}
1378
1379
Ian Rogers2c8f6532011-09-02 17:16:34 -07001380void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001381 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1382 EmitComplex(7, address, imm);
1383}
1384
1385
Ian Rogers2c8f6532011-09-02 17:16:34 -07001386void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001387 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1388 EmitUint8(0x85);
1389 EmitRegisterOperand(reg1, reg2);
1390}
1391
1392
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001393void X86Assembler::testl(Register reg, const Address& address) {
1394 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1395 EmitUint8(0x85);
1396 EmitOperand(reg, address);
1397}
1398
1399
Ian Rogers2c8f6532011-09-02 17:16:34 -07001400void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001401 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1402 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1403 // we only test the byte register to keep the encoding short.
1404 if (immediate.is_uint8() && reg < 4) {
1405 // Use zero-extended 8-bit immediate.
1406 if (reg == EAX) {
1407 EmitUint8(0xA8);
1408 } else {
1409 EmitUint8(0xF6);
1410 EmitUint8(0xC0 + reg);
1411 }
1412 EmitUint8(immediate.value() & 0xFF);
1413 } else if (reg == EAX) {
1414 // Use short form if the destination is EAX.
1415 EmitUint8(0xA9);
1416 EmitImmediate(immediate);
1417 } else {
1418 EmitUint8(0xF7);
1419 EmitOperand(0, Operand(reg));
1420 EmitImmediate(immediate);
1421 }
1422}
1423
1424
Vladimir Marko953437b2016-08-24 08:30:46 +00001425void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1426 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1427 EmitUint8(0xF6);
1428 EmitOperand(EAX, dst);
1429 CHECK(imm.is_int8());
1430 EmitUint8(imm.value() & 0xFF);
1431}
1432
1433
1434void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1435 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1436 EmitUint8(0xF7);
1437 EmitOperand(0, dst);
1438 EmitImmediate(imm);
1439}
1440
1441
Ian Rogers2c8f6532011-09-02 17:16:34 -07001442void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001443 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1444 EmitUint8(0x23);
1445 EmitOperand(dst, Operand(src));
1446}
1447
1448
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001449void X86Assembler::andl(Register reg, const Address& address) {
1450 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1451 EmitUint8(0x23);
1452 EmitOperand(reg, address);
1453}
1454
1455
Ian Rogers2c8f6532011-09-02 17:16:34 -07001456void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001457 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1458 EmitComplex(4, Operand(dst), imm);
1459}
1460
1461
Ian Rogers2c8f6532011-09-02 17:16:34 -07001462void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001463 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1464 EmitUint8(0x0B);
1465 EmitOperand(dst, Operand(src));
1466}
1467
1468
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001469void X86Assembler::orl(Register reg, const Address& address) {
1470 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1471 EmitUint8(0x0B);
1472 EmitOperand(reg, address);
1473}
1474
1475
Ian Rogers2c8f6532011-09-02 17:16:34 -07001476void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001477 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1478 EmitComplex(1, Operand(dst), imm);
1479}
1480
1481
Ian Rogers2c8f6532011-09-02 17:16:34 -07001482void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001483 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1484 EmitUint8(0x33);
1485 EmitOperand(dst, Operand(src));
1486}
1487
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001488
1489void X86Assembler::xorl(Register reg, const Address& address) {
1490 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1491 EmitUint8(0x33);
1492 EmitOperand(reg, address);
1493}
1494
1495
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01001496void X86Assembler::xorl(Register dst, const Immediate& imm) {
1497 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1498 EmitComplex(6, Operand(dst), imm);
1499}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001500
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001501
Ian Rogers2c8f6532011-09-02 17:16:34 -07001502void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1504 EmitComplex(0, Operand(reg), imm);
1505}
1506
1507
Ian Rogers2c8f6532011-09-02 17:16:34 -07001508void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001509 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1510 EmitUint8(0x01);
1511 EmitOperand(reg, address);
1512}
1513
1514
Ian Rogers2c8f6532011-09-02 17:16:34 -07001515void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001516 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1517 EmitComplex(0, address, imm);
1518}
1519
1520
Ian Rogers2c8f6532011-09-02 17:16:34 -07001521void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001522 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1523 EmitComplex(2, Operand(reg), imm);
1524}
1525
1526
Ian Rogers2c8f6532011-09-02 17:16:34 -07001527void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001528 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1529 EmitUint8(0x13);
1530 EmitOperand(dst, Operand(src));
1531}
1532
1533
Ian Rogers2c8f6532011-09-02 17:16:34 -07001534void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1536 EmitUint8(0x13);
1537 EmitOperand(dst, address);
1538}
1539
1540
Ian Rogers2c8f6532011-09-02 17:16:34 -07001541void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001542 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1543 EmitUint8(0x2B);
1544 EmitOperand(dst, Operand(src));
1545}
1546
1547
Ian Rogers2c8f6532011-09-02 17:16:34 -07001548void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001549 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1550 EmitComplex(5, Operand(reg), imm);
1551}
1552
1553
Ian Rogers2c8f6532011-09-02 17:16:34 -07001554void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001555 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1556 EmitUint8(0x2B);
1557 EmitOperand(reg, address);
1558}
1559
1560
Mark Mendell09ed1a32015-03-25 08:30:06 -04001561void X86Assembler::subl(const Address& address, Register reg) {
1562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1563 EmitUint8(0x29);
1564 EmitOperand(reg, address);
1565}
1566
1567
Ian Rogers2c8f6532011-09-02 17:16:34 -07001568void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001569 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1570 EmitUint8(0x99);
1571}
1572
1573
Ian Rogers2c8f6532011-09-02 17:16:34 -07001574void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001575 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1576 EmitUint8(0xF7);
1577 EmitUint8(0xF8 | reg);
1578}
1579
1580
Ian Rogers2c8f6532011-09-02 17:16:34 -07001581void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001582 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1583 EmitUint8(0x0F);
1584 EmitUint8(0xAF);
1585 EmitOperand(dst, Operand(src));
1586}
1587
1588
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001589void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001590 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001591 // See whether imm can be represented as a sign-extended 8bit value.
1592 int32_t v32 = static_cast<int32_t>(imm.value());
1593 if (IsInt<8>(v32)) {
1594 // Sign-extension works.
1595 EmitUint8(0x6B);
1596 EmitOperand(dst, Operand(src));
1597 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
1598 } else {
1599 // Not representable, use full immediate.
1600 EmitUint8(0x69);
1601 EmitOperand(dst, Operand(src));
1602 EmitImmediate(imm);
1603 }
1604}
1605
1606
1607void X86Assembler::imull(Register reg, const Immediate& imm) {
1608 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001609}
1610
1611
Ian Rogers2c8f6532011-09-02 17:16:34 -07001612void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001613 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1614 EmitUint8(0x0F);
1615 EmitUint8(0xAF);
1616 EmitOperand(reg, address);
1617}
1618
1619
Ian Rogers2c8f6532011-09-02 17:16:34 -07001620void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001621 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1622 EmitUint8(0xF7);
1623 EmitOperand(5, Operand(reg));
1624}
1625
1626
Ian Rogers2c8f6532011-09-02 17:16:34 -07001627void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1629 EmitUint8(0xF7);
1630 EmitOperand(5, address);
1631}
1632
1633
Ian Rogers2c8f6532011-09-02 17:16:34 -07001634void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001635 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1636 EmitUint8(0xF7);
1637 EmitOperand(4, Operand(reg));
1638}
1639
1640
Ian Rogers2c8f6532011-09-02 17:16:34 -07001641void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001642 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1643 EmitUint8(0xF7);
1644 EmitOperand(4, address);
1645}
1646
1647
Ian Rogers2c8f6532011-09-02 17:16:34 -07001648void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001649 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1650 EmitUint8(0x1B);
1651 EmitOperand(dst, Operand(src));
1652}
1653
1654
Ian Rogers2c8f6532011-09-02 17:16:34 -07001655void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001656 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1657 EmitComplex(3, Operand(reg), imm);
1658}
1659
1660
Ian Rogers2c8f6532011-09-02 17:16:34 -07001661void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001662 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1663 EmitUint8(0x1B);
1664 EmitOperand(dst, address);
1665}
1666
1667
Mark Mendell09ed1a32015-03-25 08:30:06 -04001668void X86Assembler::sbbl(const Address& address, Register src) {
1669 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1670 EmitUint8(0x19);
1671 EmitOperand(src, address);
1672}
1673
1674
Ian Rogers2c8f6532011-09-02 17:16:34 -07001675void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001676 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1677 EmitUint8(0x40 + reg);
1678}
1679
1680
Ian Rogers2c8f6532011-09-02 17:16:34 -07001681void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1683 EmitUint8(0xFF);
1684 EmitOperand(0, address);
1685}
1686
1687
Ian Rogers2c8f6532011-09-02 17:16:34 -07001688void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001689 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1690 EmitUint8(0x48 + reg);
1691}
1692
1693
Ian Rogers2c8f6532011-09-02 17:16:34 -07001694void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001695 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1696 EmitUint8(0xFF);
1697 EmitOperand(1, address);
1698}
1699
1700
Ian Rogers2c8f6532011-09-02 17:16:34 -07001701void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001702 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001703}
1704
1705
Ian Rogers2c8f6532011-09-02 17:16:34 -07001706void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001707 EmitGenericShift(4, Operand(operand), shifter);
1708}
1709
1710
1711void X86Assembler::shll(const Address& address, const Immediate& imm) {
1712 EmitGenericShift(4, address, imm);
1713}
1714
1715
1716void X86Assembler::shll(const Address& address, Register shifter) {
1717 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001718}
1719
1720
Ian Rogers2c8f6532011-09-02 17:16:34 -07001721void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001722 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001723}
1724
1725
Ian Rogers2c8f6532011-09-02 17:16:34 -07001726void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001727 EmitGenericShift(5, Operand(operand), shifter);
1728}
1729
1730
1731void X86Assembler::shrl(const Address& address, const Immediate& imm) {
1732 EmitGenericShift(5, address, imm);
1733}
1734
1735
1736void X86Assembler::shrl(const Address& address, Register shifter) {
1737 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001738}
1739
1740
Ian Rogers2c8f6532011-09-02 17:16:34 -07001741void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001742 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001743}
1744
1745
Ian Rogers2c8f6532011-09-02 17:16:34 -07001746void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001747 EmitGenericShift(7, Operand(operand), shifter);
1748}
1749
1750
1751void X86Assembler::sarl(const Address& address, const Immediate& imm) {
1752 EmitGenericShift(7, address, imm);
1753}
1754
1755
1756void X86Assembler::sarl(const Address& address, Register shifter) {
1757 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001758}
1759
1760
Calin Juravle9aec02f2014-11-18 23:06:35 +00001761void X86Assembler::shld(Register dst, Register src, Register shifter) {
1762 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1764 EmitUint8(0x0F);
1765 EmitUint8(0xA5);
1766 EmitRegisterOperand(src, dst);
1767}
1768
1769
Mark P Mendell73945692015-04-29 14:56:17 +00001770void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
1771 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1772 EmitUint8(0x0F);
1773 EmitUint8(0xA4);
1774 EmitRegisterOperand(src, dst);
1775 EmitUint8(imm.value() & 0xFF);
1776}
1777
1778
Calin Juravle9aec02f2014-11-18 23:06:35 +00001779void X86Assembler::shrd(Register dst, Register src, Register shifter) {
1780 DCHECK_EQ(ECX, shifter);
1781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1782 EmitUint8(0x0F);
1783 EmitUint8(0xAD);
1784 EmitRegisterOperand(src, dst);
1785}
1786
1787
Mark P Mendell73945692015-04-29 14:56:17 +00001788void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
1789 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1790 EmitUint8(0x0F);
1791 EmitUint8(0xAC);
1792 EmitRegisterOperand(src, dst);
1793 EmitUint8(imm.value() & 0xFF);
1794}
1795
1796
Mark Mendellbcee0922015-09-15 21:45:01 -04001797void X86Assembler::roll(Register reg, const Immediate& imm) {
1798 EmitGenericShift(0, Operand(reg), imm);
1799}
1800
1801
1802void X86Assembler::roll(Register operand, Register shifter) {
1803 EmitGenericShift(0, Operand(operand), shifter);
1804}
1805
1806
1807void X86Assembler::rorl(Register reg, const Immediate& imm) {
1808 EmitGenericShift(1, Operand(reg), imm);
1809}
1810
1811
1812void X86Assembler::rorl(Register operand, Register shifter) {
1813 EmitGenericShift(1, Operand(operand), shifter);
1814}
1815
1816
Ian Rogers2c8f6532011-09-02 17:16:34 -07001817void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001818 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1819 EmitUint8(0xF7);
1820 EmitOperand(3, Operand(reg));
1821}
1822
1823
Ian Rogers2c8f6532011-09-02 17:16:34 -07001824void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001825 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1826 EmitUint8(0xF7);
1827 EmitUint8(0xD0 | reg);
1828}
1829
1830
Ian Rogers2c8f6532011-09-02 17:16:34 -07001831void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001832 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1833 EmitUint8(0xC8);
1834 CHECK(imm.is_uint16());
1835 EmitUint8(imm.value() & 0xFF);
1836 EmitUint8((imm.value() >> 8) & 0xFF);
1837 EmitUint8(0x00);
1838}
1839
1840
Ian Rogers2c8f6532011-09-02 17:16:34 -07001841void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001842 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1843 EmitUint8(0xC9);
1844}
1845
1846
Ian Rogers2c8f6532011-09-02 17:16:34 -07001847void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001848 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1849 EmitUint8(0xC3);
1850}
1851
1852
Ian Rogers2c8f6532011-09-02 17:16:34 -07001853void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001854 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1855 EmitUint8(0xC2);
1856 CHECK(imm.is_uint16());
1857 EmitUint8(imm.value() & 0xFF);
1858 EmitUint8((imm.value() >> 8) & 0xFF);
1859}
1860
1861
1862
Ian Rogers2c8f6532011-09-02 17:16:34 -07001863void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001864 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1865 EmitUint8(0x90);
1866}
1867
1868
Ian Rogers2c8f6532011-09-02 17:16:34 -07001869void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001870 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1871 EmitUint8(0xCC);
1872}
1873
1874
Ian Rogers2c8f6532011-09-02 17:16:34 -07001875void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001876 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1877 EmitUint8(0xF4);
1878}
1879
1880
Ian Rogers2c8f6532011-09-02 17:16:34 -07001881void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001882 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1883 if (label->IsBound()) {
1884 static const int kShortSize = 2;
1885 static const int kLongSize = 6;
1886 int offset = label->Position() - buffer_.Size();
1887 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08001888 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001889 EmitUint8(0x70 + condition);
1890 EmitUint8((offset - kShortSize) & 0xFF);
1891 } else {
1892 EmitUint8(0x0F);
1893 EmitUint8(0x80 + condition);
1894 EmitInt32(offset - kLongSize);
1895 }
1896 } else {
1897 EmitUint8(0x0F);
1898 EmitUint8(0x80 + condition);
1899 EmitLabelLink(label);
1900 }
1901}
1902
1903
Mark Mendell73f455e2015-08-21 09:30:05 -04001904void X86Assembler::j(Condition condition, NearLabel* label) {
1905 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1906 if (label->IsBound()) {
1907 static const int kShortSize = 2;
1908 int offset = label->Position() - buffer_.Size();
1909 CHECK_LE(offset, 0);
1910 CHECK(IsInt<8>(offset - kShortSize));
1911 EmitUint8(0x70 + condition);
1912 EmitUint8((offset - kShortSize) & 0xFF);
1913 } else {
1914 EmitUint8(0x70 + condition);
1915 EmitLabelLink(label);
1916 }
1917}
1918
1919
1920void X86Assembler::jecxz(NearLabel* label) {
1921 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1922 if (label->IsBound()) {
1923 static const int kShortSize = 2;
1924 int offset = label->Position() - buffer_.Size();
1925 CHECK_LE(offset, 0);
1926 CHECK(IsInt<8>(offset - kShortSize));
1927 EmitUint8(0xE3);
1928 EmitUint8((offset - kShortSize) & 0xFF);
1929 } else {
1930 EmitUint8(0xE3);
1931 EmitLabelLink(label);
1932 }
1933}
1934
1935
Ian Rogers2c8f6532011-09-02 17:16:34 -07001936void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001937 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1938 EmitUint8(0xFF);
1939 EmitRegisterOperand(4, reg);
1940}
1941
Ian Rogers7caad772012-03-30 01:07:54 -07001942void X86Assembler::jmp(const Address& address) {
1943 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1944 EmitUint8(0xFF);
1945 EmitOperand(4, address);
1946}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001947
Ian Rogers2c8f6532011-09-02 17:16:34 -07001948void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001949 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1950 if (label->IsBound()) {
1951 static const int kShortSize = 2;
1952 static const int kLongSize = 5;
1953 int offset = label->Position() - buffer_.Size();
1954 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08001955 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001956 EmitUint8(0xEB);
1957 EmitUint8((offset - kShortSize) & 0xFF);
1958 } else {
1959 EmitUint8(0xE9);
1960 EmitInt32(offset - kLongSize);
1961 }
1962 } else {
1963 EmitUint8(0xE9);
1964 EmitLabelLink(label);
1965 }
1966}
1967
1968
Mark Mendell73f455e2015-08-21 09:30:05 -04001969void X86Assembler::jmp(NearLabel* label) {
1970 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1971 if (label->IsBound()) {
1972 static const int kShortSize = 2;
1973 int offset = label->Position() - buffer_.Size();
1974 CHECK_LE(offset, 0);
1975 CHECK(IsInt<8>(offset - kShortSize));
1976 EmitUint8(0xEB);
1977 EmitUint8((offset - kShortSize) & 0xFF);
1978 } else {
1979 EmitUint8(0xEB);
1980 EmitLabelLink(label);
1981 }
1982}
1983
1984
jessicahandojob03d6402016-09-07 12:16:53 -07001985void X86Assembler::repne_scasb() {
1986 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1987 EmitUint8(0xF2);
1988 EmitUint8(0xAE);
1989}
1990
1991
Andreas Gampe21030dd2015-05-07 14:46:15 -07001992void X86Assembler::repne_scasw() {
1993 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1994 EmitUint8(0x66);
1995 EmitUint8(0xF2);
1996 EmitUint8(0xAF);
1997}
1998
1999
jessicahandojob03d6402016-09-07 12:16:53 -07002000void X86Assembler::repe_cmpsb() {
2001 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2002 EmitUint8(0xF2);
2003 EmitUint8(0xA6);
2004}
2005
2006
agicsaki71311f82015-07-27 11:34:13 -07002007void X86Assembler::repe_cmpsw() {
2008 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2009 EmitUint8(0x66);
2010 EmitUint8(0xF3);
2011 EmitUint8(0xA7);
2012}
2013
2014
agicsaki970abfb2015-07-31 10:31:14 -07002015void X86Assembler::repe_cmpsl() {
2016 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2017 EmitUint8(0xF3);
2018 EmitUint8(0xA7);
2019}
2020
2021
jessicahandojob03d6402016-09-07 12:16:53 -07002022void X86Assembler::rep_movsb() {
2023 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2024 EmitUint8(0xF3);
2025 EmitUint8(0xA4);
2026}
2027
2028
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002029void X86Assembler::rep_movsw() {
2030 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2031 EmitUint8(0x66);
2032 EmitUint8(0xF3);
2033 EmitUint8(0xA5);
2034}
2035
2036
Ian Rogers2c8f6532011-09-02 17:16:34 -07002037X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002038 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2039 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002040 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002041}
2042
2043
Ian Rogers2c8f6532011-09-02 17:16:34 -07002044void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002045 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2046 EmitUint8(0x0F);
2047 EmitUint8(0xB1);
2048 EmitOperand(reg, address);
2049}
2050
Mark Mendell58d25fd2015-04-03 14:52:31 -04002051
2052void X86Assembler::cmpxchg8b(const Address& address) {
2053 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2054 EmitUint8(0x0F);
2055 EmitUint8(0xC7);
2056 EmitOperand(1, address);
2057}
2058
2059
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002060void X86Assembler::mfence() {
2061 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2062 EmitUint8(0x0F);
2063 EmitUint8(0xAE);
2064 EmitUint8(0xF0);
2065}
2066
Ian Rogers2c8f6532011-09-02 17:16:34 -07002067X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002068 // TODO: fs is a prefix and not an instruction
2069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2070 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002071 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002072}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002073
Ian Rogersbefbd572014-03-06 01:13:39 -08002074X86Assembler* X86Assembler::gs() {
2075 // TODO: fs is a prefix and not an instruction
2076 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2077 EmitUint8(0x65);
2078 return this;
2079}
2080
Ian Rogers2c8f6532011-09-02 17:16:34 -07002081void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002082 int value = imm.value();
2083 if (value > 0) {
2084 if (value == 1) {
2085 incl(reg);
2086 } else if (value != 0) {
2087 addl(reg, imm);
2088 }
2089 } else if (value < 0) {
2090 value = -value;
2091 if (value == 1) {
2092 decl(reg);
2093 } else if (value != 0) {
2094 subl(reg, Immediate(value));
2095 }
2096 }
2097}
2098
2099
Roland Levillain647b9ed2014-11-27 12:06:00 +00002100void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2101 // TODO: Need to have a code constants table.
2102 pushl(Immediate(High32Bits(value)));
2103 pushl(Immediate(Low32Bits(value)));
2104 movsd(dst, Address(ESP, 0));
2105 addl(ESP, Immediate(2 * sizeof(int32_t)));
2106}
2107
2108
Ian Rogers2c8f6532011-09-02 17:16:34 -07002109void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002110 // TODO: Need to have a code constants table.
2111 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002112 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002113}
2114
2115
Ian Rogers2c8f6532011-09-02 17:16:34 -07002116void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002117 CHECK(IsPowerOfTwo(alignment));
2118 // Emit nop instruction until the real position is aligned.
2119 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2120 nop();
2121 }
2122}
2123
2124
Ian Rogers2c8f6532011-09-02 17:16:34 -07002125void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002126 int bound = buffer_.Size();
2127 CHECK(!label->IsBound()); // Labels can only be bound once.
2128 while (label->IsLinked()) {
2129 int position = label->LinkPosition();
2130 int next = buffer_.Load<int32_t>(position);
2131 buffer_.Store<int32_t>(position, bound - (position + 4));
2132 label->position_ = next;
2133 }
2134 label->BindTo(bound);
2135}
2136
2137
Mark Mendell73f455e2015-08-21 09:30:05 -04002138void X86Assembler::Bind(NearLabel* label) {
2139 int bound = buffer_.Size();
2140 CHECK(!label->IsBound()); // Labels can only be bound once.
2141 while (label->IsLinked()) {
2142 int position = label->LinkPosition();
2143 uint8_t delta = buffer_.Load<uint8_t>(position);
2144 int offset = bound - (position + 1);
2145 CHECK(IsInt<8>(offset));
2146 buffer_.Store<int8_t>(position, offset);
2147 label->position_ = delta != 0u ? label->position_ - delta : 0;
2148 }
2149 label->BindTo(bound);
2150}
2151
2152
Ian Rogers44fb0d02012-03-23 16:46:24 -07002153void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2154 CHECK_GE(reg_or_opcode, 0);
2155 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002156 const int length = operand.length_;
2157 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002158 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002159 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002160 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002161 // Emit the rest of the encoded operand.
2162 for (int i = 1; i < length; i++) {
2163 EmitUint8(operand.encoding_[i]);
2164 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002165 AssemblerFixup* fixup = operand.GetFixup();
2166 if (fixup != nullptr) {
2167 EmitFixup(fixup);
2168 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002169}
2170
2171
Ian Rogers2c8f6532011-09-02 17:16:34 -07002172void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002173 EmitInt32(imm.value());
2174}
2175
2176
Ian Rogers44fb0d02012-03-23 16:46:24 -07002177void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002178 const Operand& operand,
2179 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002180 CHECK_GE(reg_or_opcode, 0);
2181 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002182 if (immediate.is_int8()) {
2183 // Use sign-extended 8-bit immediate.
2184 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002185 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002186 EmitUint8(immediate.value() & 0xFF);
2187 } else if (operand.IsRegister(EAX)) {
2188 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002189 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002190 EmitImmediate(immediate);
2191 } else {
2192 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002193 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002194 EmitImmediate(immediate);
2195 }
2196}
2197
2198
Ian Rogers2c8f6532011-09-02 17:16:34 -07002199void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002200 if (label->IsBound()) {
2201 int offset = label->Position() - buffer_.Size();
2202 CHECK_LE(offset, 0);
2203 EmitInt32(offset - instruction_size);
2204 } else {
2205 EmitLabelLink(label);
2206 }
2207}
2208
2209
Ian Rogers2c8f6532011-09-02 17:16:34 -07002210void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002211 CHECK(!label->IsBound());
2212 int position = buffer_.Size();
2213 EmitInt32(label->position_);
2214 label->LinkTo(position);
2215}
2216
2217
Mark Mendell73f455e2015-08-21 09:30:05 -04002218void X86Assembler::EmitLabelLink(NearLabel* label) {
2219 CHECK(!label->IsBound());
2220 int position = buffer_.Size();
2221 if (label->IsLinked()) {
2222 // Save the delta in the byte that we have to play with.
2223 uint32_t delta = position - label->LinkPosition();
2224 CHECK(IsUint<8>(delta));
2225 EmitUint8(delta & 0xFF);
2226 } else {
2227 EmitUint8(0);
2228 }
2229 label->LinkTo(position);
2230}
2231
2232
Ian Rogers44fb0d02012-03-23 16:46:24 -07002233void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002234 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002235 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002236 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2237 CHECK(imm.is_int8());
2238 if (imm.value() == 1) {
2239 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002240 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002241 } else {
2242 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002243 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002244 EmitUint8(imm.value() & 0xFF);
2245 }
2246}
2247
2248
Ian Rogers44fb0d02012-03-23 16:46:24 -07002249void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002250 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002251 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2253 CHECK_EQ(shifter, ECX);
2254 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002255 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002256}
2257
Mark Mendell0616ae02015-04-17 12:49:27 -04002258void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002259 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002260 // Generate the data for the literal area.
2261 for (size_t i = 0, e = area.size(); i < e; i++) {
2262 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2263 EmitInt32(area[i]);
2264 }
2265}
2266
Mark Mendell805b3b52015-09-18 14:10:29 -04002267size_t ConstantArea::AppendInt32(int32_t v) {
2268 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002269 buffer_.push_back(v);
2270 return result;
2271}
2272
Mark Mendell805b3b52015-09-18 14:10:29 -04002273size_t ConstantArea::AddInt32(int32_t v) {
2274 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2275 if (v == buffer_[i]) {
2276 return i * elem_size_;
2277 }
2278 }
2279
2280 // Didn't match anything.
2281 return AppendInt32(v);
2282}
2283
2284size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002285 int32_t v_low = Low32Bits(v);
2286 int32_t v_high = High32Bits(v);
2287 if (buffer_.size() > 1) {
2288 // Ensure we don't pass the end of the buffer.
2289 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2290 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002291 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002292 }
2293 }
2294 }
2295
2296 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002297 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002298 buffer_.push_back(v_low);
2299 buffer_.push_back(v_high);
2300 return result;
2301}
2302
Mark Mendell805b3b52015-09-18 14:10:29 -04002303size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002304 // Treat the value as a 64-bit integer value.
2305 return AddInt64(bit_cast<int64_t, double>(v));
2306}
2307
Mark Mendell805b3b52015-09-18 14:10:29 -04002308size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002309 // Treat the value as a 32-bit integer value.
2310 return AddInt32(bit_cast<int32_t, float>(v));
2311}
2312
Ian Rogers2c8f6532011-09-02 17:16:34 -07002313} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002314} // namespace art