Elliott Hughes | 2faa5f1 | 2012-01-30 14:42:07 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 16 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 17 | #include "assembler_x86.h" |
| 18 | |
Elliott Hughes | 1aa246d | 2012-12-13 09:29:36 -0800 | [diff] [blame] | 19 | #include "base/casts.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 20 | #include "entrypoints/quick/quick_entrypoints.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 21 | #include "memory_region.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 22 | #include "thread.h" |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 23 | |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 24 | namespace art { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 25 | namespace x86 { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 26 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 27 | std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { |
| 28 | return os << "XMM" << static_cast<int>(reg); |
| 29 | } |
| 30 | |
| 31 | std::ostream& operator<<(std::ostream& os, const X87Register& reg) { |
| 32 | return os << "ST" << static_cast<int>(reg); |
| 33 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 34 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 35 | void X86Assembler::call(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 36 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 37 | EmitUint8(0xFF); |
| 38 | EmitRegisterOperand(2, reg); |
| 39 | } |
| 40 | |
| 41 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 42 | void X86Assembler::call(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 43 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 44 | EmitUint8(0xFF); |
| 45 | EmitOperand(2, address); |
| 46 | } |
| 47 | |
| 48 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 49 | void X86Assembler::call(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 50 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 51 | EmitUint8(0xE8); |
| 52 | static const int kSize = 5; |
Nicolas Geoffray | 1cf9528 | 2014-12-12 19:22:03 +0000 | [diff] [blame] | 53 | // Offset by one because we already have emitted the opcode. |
| 54 | EmitLabel(label, kSize - 1); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | |
Nicolas Geoffray | 8ccc3f5 | 2014-03-19 10:34:11 +0000 | [diff] [blame] | 58 | void X86Assembler::call(const ExternalLabel& label) { |
| 59 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 60 | intptr_t call_start = buffer_.GetPosition(); |
| 61 | EmitUint8(0xE8); |
| 62 | EmitInt32(label.address()); |
| 63 | static const intptr_t kCallExternalLabelSize = 5; |
| 64 | DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize); |
| 65 | } |
| 66 | |
| 67 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 68 | void X86Assembler::pushl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 69 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 70 | EmitUint8(0x50 + reg); |
| 71 | } |
| 72 | |
| 73 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 74 | void X86Assembler::pushl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 75 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 76 | EmitUint8(0xFF); |
| 77 | EmitOperand(6, address); |
| 78 | } |
| 79 | |
| 80 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 81 | void X86Assembler::pushl(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 82 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 83 | if (imm.is_int8()) { |
| 84 | EmitUint8(0x6A); |
| 85 | EmitUint8(imm.value() & 0xFF); |
| 86 | } else { |
| 87 | EmitUint8(0x68); |
| 88 | EmitImmediate(imm); |
| 89 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 93 | void X86Assembler::popl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 94 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 95 | EmitUint8(0x58 + reg); |
| 96 | } |
| 97 | |
| 98 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 99 | void X86Assembler::popl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 100 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 101 | EmitUint8(0x8F); |
| 102 | EmitOperand(0, address); |
| 103 | } |
| 104 | |
| 105 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 106 | void X86Assembler::movl(Register dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 107 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 108 | EmitUint8(0xB8 + dst); |
| 109 | EmitImmediate(imm); |
| 110 | } |
| 111 | |
| 112 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 113 | void X86Assembler::movl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 114 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 115 | EmitUint8(0x89); |
| 116 | EmitRegisterOperand(src, dst); |
| 117 | } |
| 118 | |
| 119 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 120 | void X86Assembler::movl(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 121 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 122 | EmitUint8(0x8B); |
| 123 | EmitOperand(dst, src); |
| 124 | } |
| 125 | |
| 126 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 127 | void X86Assembler::movl(const Address& dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 128 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 129 | EmitUint8(0x89); |
| 130 | EmitOperand(src, dst); |
| 131 | } |
| 132 | |
| 133 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 134 | void X86Assembler::movl(const Address& dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 135 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 136 | EmitUint8(0xC7); |
| 137 | EmitOperand(0, dst); |
| 138 | EmitImmediate(imm); |
| 139 | } |
| 140 | |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 141 | void X86Assembler::movl(const Address& dst, Label* lbl) { |
| 142 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 143 | EmitUint8(0xC7); |
| 144 | EmitOperand(0, dst); |
| 145 | EmitLabel(lbl, dst.length_ + 5); |
| 146 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 147 | |
Mark Mendell | 7a08fb5 | 2015-07-15 14:09:35 -0400 | [diff] [blame] | 148 | void X86Assembler::movntl(const Address& dst, Register src) { |
| 149 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 150 | EmitUint8(0x0F); |
| 151 | EmitUint8(0xC3); |
| 152 | EmitOperand(src, dst); |
| 153 | } |
| 154 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 155 | void X86Assembler::bswapl(Register dst) { |
| 156 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 157 | EmitUint8(0x0F); |
| 158 | EmitUint8(0xC8 + dst); |
| 159 | } |
| 160 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 161 | void X86Assembler::bsfl(Register dst, Register src) { |
| 162 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 163 | EmitUint8(0x0F); |
| 164 | EmitUint8(0xBC); |
| 165 | EmitRegisterOperand(dst, src); |
| 166 | } |
| 167 | |
| 168 | void X86Assembler::bsfl(Register dst, const Address& src) { |
| 169 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 170 | EmitUint8(0x0F); |
| 171 | EmitUint8(0xBC); |
| 172 | EmitOperand(dst, src); |
| 173 | } |
| 174 | |
Mark Mendell | 8ae3ffb | 2015-08-12 21:16:41 -0400 | [diff] [blame] | 175 | void X86Assembler::bsrl(Register dst, Register src) { |
| 176 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 177 | EmitUint8(0x0F); |
| 178 | EmitUint8(0xBD); |
| 179 | EmitRegisterOperand(dst, src); |
| 180 | } |
| 181 | |
| 182 | void X86Assembler::bsrl(Register dst, const Address& src) { |
| 183 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 184 | EmitUint8(0x0F); |
| 185 | EmitUint8(0xBD); |
| 186 | EmitOperand(dst, src); |
| 187 | } |
| 188 | |
Aart Bik | c39dac1 | 2016-01-21 08:59:48 -0800 | [diff] [blame] | 189 | void X86Assembler::popcntl(Register dst, Register src) { |
| 190 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 191 | EmitUint8(0xF3); |
| 192 | EmitUint8(0x0F); |
| 193 | EmitUint8(0xB8); |
| 194 | EmitRegisterOperand(dst, src); |
| 195 | } |
| 196 | |
| 197 | void X86Assembler::popcntl(Register dst, const Address& src) { |
| 198 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 199 | EmitUint8(0xF3); |
| 200 | EmitUint8(0x0F); |
| 201 | EmitUint8(0xB8); |
| 202 | EmitOperand(dst, src); |
| 203 | } |
| 204 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 205 | void X86Assembler::movzxb(Register dst, ByteRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 206 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 207 | EmitUint8(0x0F); |
| 208 | EmitUint8(0xB6); |
| 209 | EmitRegisterOperand(dst, src); |
| 210 | } |
| 211 | |
| 212 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 213 | void X86Assembler::movzxb(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 214 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 215 | EmitUint8(0x0F); |
| 216 | EmitUint8(0xB6); |
| 217 | EmitOperand(dst, src); |
| 218 | } |
| 219 | |
| 220 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 221 | void X86Assembler::movsxb(Register dst, ByteRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 222 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 223 | EmitUint8(0x0F); |
| 224 | EmitUint8(0xBE); |
| 225 | EmitRegisterOperand(dst, src); |
| 226 | } |
| 227 | |
| 228 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 229 | void X86Assembler::movsxb(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 230 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 231 | EmitUint8(0x0F); |
| 232 | EmitUint8(0xBE); |
| 233 | EmitOperand(dst, src); |
| 234 | } |
| 235 | |
| 236 | |
Elliott Hughes | 1bac54f | 2012-03-16 12:48:31 -0700 | [diff] [blame] | 237 | void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 238 | LOG(FATAL) << "Use movzxb or movsxb instead."; |
| 239 | } |
| 240 | |
| 241 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 242 | void X86Assembler::movb(const Address& dst, ByteRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 243 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 244 | EmitUint8(0x88); |
| 245 | EmitOperand(src, dst); |
| 246 | } |
| 247 | |
| 248 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 249 | void X86Assembler::movb(const Address& dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 250 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 251 | EmitUint8(0xC6); |
| 252 | EmitOperand(EAX, dst); |
| 253 | CHECK(imm.is_int8()); |
| 254 | EmitUint8(imm.value() & 0xFF); |
| 255 | } |
| 256 | |
| 257 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 258 | void X86Assembler::movzxw(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 259 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 260 | EmitUint8(0x0F); |
| 261 | EmitUint8(0xB7); |
| 262 | EmitRegisterOperand(dst, src); |
| 263 | } |
| 264 | |
| 265 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 266 | void X86Assembler::movzxw(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 267 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 268 | EmitUint8(0x0F); |
| 269 | EmitUint8(0xB7); |
| 270 | EmitOperand(dst, src); |
| 271 | } |
| 272 | |
| 273 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 274 | void X86Assembler::movsxw(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 275 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 276 | EmitUint8(0x0F); |
| 277 | EmitUint8(0xBF); |
| 278 | EmitRegisterOperand(dst, src); |
| 279 | } |
| 280 | |
| 281 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 282 | void X86Assembler::movsxw(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 283 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 284 | EmitUint8(0x0F); |
| 285 | EmitUint8(0xBF); |
| 286 | EmitOperand(dst, src); |
| 287 | } |
| 288 | |
| 289 | |
Elliott Hughes | 1bac54f | 2012-03-16 12:48:31 -0700 | [diff] [blame] | 290 | void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 291 | LOG(FATAL) << "Use movzxw or movsxw instead."; |
| 292 | } |
| 293 | |
| 294 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 295 | void X86Assembler::movw(const Address& dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 296 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 297 | EmitOperandSizeOverride(); |
| 298 | EmitUint8(0x89); |
| 299 | EmitOperand(src, dst); |
| 300 | } |
| 301 | |
| 302 | |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 303 | void X86Assembler::movw(const Address& dst, const Immediate& imm) { |
| 304 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 305 | EmitOperandSizeOverride(); |
| 306 | EmitUint8(0xC7); |
| 307 | EmitOperand(0, dst); |
Nicolas Geoffray | b6e7206 | 2014-10-07 14:54:48 +0100 | [diff] [blame] | 308 | CHECK(imm.is_uint16() || imm.is_int16()); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 309 | EmitUint8(imm.value() & 0xFF); |
| 310 | EmitUint8(imm.value() >> 8); |
| 311 | } |
| 312 | |
| 313 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 314 | void X86Assembler::leal(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 315 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 316 | EmitUint8(0x8D); |
| 317 | EmitOperand(dst, src); |
| 318 | } |
| 319 | |
| 320 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 321 | void X86Assembler::cmovl(Condition condition, Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 322 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 323 | EmitUint8(0x0F); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 324 | EmitUint8(0x40 + condition); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 325 | EmitRegisterOperand(dst, src); |
| 326 | } |
| 327 | |
| 328 | |
Mark Mendell | abdac47 | 2016-02-12 13:49:03 -0500 | [diff] [blame] | 329 | void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) { |
| 330 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 331 | EmitUint8(0x0F); |
| 332 | EmitUint8(0x40 + condition); |
| 333 | EmitOperand(dst, src); |
| 334 | } |
| 335 | |
| 336 | |
Nicolas Geoffray | 5b4b898 | 2014-12-18 17:45:56 +0000 | [diff] [blame] | 337 | void X86Assembler::setb(Condition condition, Register dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 338 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 339 | EmitUint8(0x0F); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 340 | EmitUint8(0x90 + condition); |
Nicolas Geoffray | 5b4b898 | 2014-12-18 17:45:56 +0000 | [diff] [blame] | 341 | EmitOperand(0, Operand(dst)); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 345 | void X86Assembler::movaps(XmmRegister dst, XmmRegister src) { |
| 346 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 347 | EmitUint8(0x0F); |
| 348 | EmitUint8(0x28); |
| 349 | EmitXmmRegisterOperand(dst, src); |
| 350 | } |
| 351 | |
| 352 | |
Aart Bik | c778226 | 2017-01-13 16:20:08 -0800 | [diff] [blame] | 353 | void X86Assembler::movaps(XmmRegister dst, const Address& src) { |
| 354 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 355 | EmitUint8(0x0F); |
| 356 | EmitUint8(0x28); |
| 357 | EmitOperand(dst, src); |
| 358 | } |
| 359 | |
| 360 | |
| 361 | void X86Assembler::movups(XmmRegister dst, const Address& src) { |
| 362 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 363 | EmitUint8(0x0F); |
| 364 | EmitUint8(0x10); |
| 365 | EmitOperand(dst, src); |
| 366 | } |
| 367 | |
| 368 | |
| 369 | void X86Assembler::movaps(const Address& dst, XmmRegister src) { |
| 370 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 371 | EmitUint8(0x0F); |
| 372 | EmitUint8(0x29); |
| 373 | EmitOperand(src, dst); |
| 374 | } |
| 375 | |
| 376 | |
| 377 | void X86Assembler::movups(const Address& dst, XmmRegister src) { |
| 378 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 379 | EmitUint8(0x0F); |
| 380 | EmitUint8(0x11); |
| 381 | EmitOperand(src, dst); |
| 382 | } |
| 383 | |
| 384 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 385 | void X86Assembler::movss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 386 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 387 | EmitUint8(0xF3); |
| 388 | EmitUint8(0x0F); |
| 389 | EmitUint8(0x10); |
| 390 | EmitOperand(dst, src); |
| 391 | } |
| 392 | |
| 393 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 394 | void X86Assembler::movss(const Address& dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 395 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 396 | EmitUint8(0xF3); |
| 397 | EmitUint8(0x0F); |
| 398 | EmitUint8(0x11); |
| 399 | EmitOperand(src, dst); |
| 400 | } |
| 401 | |
| 402 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 403 | void X86Assembler::movss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 404 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 405 | EmitUint8(0xF3); |
| 406 | EmitUint8(0x0F); |
| 407 | EmitUint8(0x11); |
| 408 | EmitXmmRegisterOperand(src, dst); |
| 409 | } |
| 410 | |
| 411 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 412 | void X86Assembler::movd(XmmRegister dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 413 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 414 | EmitUint8(0x66); |
| 415 | EmitUint8(0x0F); |
| 416 | EmitUint8(0x6E); |
| 417 | EmitOperand(dst, Operand(src)); |
| 418 | } |
| 419 | |
| 420 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 421 | void X86Assembler::movd(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 422 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 423 | EmitUint8(0x66); |
| 424 | EmitUint8(0x0F); |
| 425 | EmitUint8(0x7E); |
| 426 | EmitOperand(src, Operand(dst)); |
| 427 | } |
| 428 | |
| 429 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 430 | void X86Assembler::addss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 431 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 432 | EmitUint8(0xF3); |
| 433 | EmitUint8(0x0F); |
| 434 | EmitUint8(0x58); |
| 435 | EmitXmmRegisterOperand(dst, src); |
| 436 | } |
| 437 | |
| 438 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 439 | void X86Assembler::addss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 440 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 441 | EmitUint8(0xF3); |
| 442 | EmitUint8(0x0F); |
| 443 | EmitUint8(0x58); |
| 444 | EmitOperand(dst, src); |
| 445 | } |
| 446 | |
| 447 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 448 | void X86Assembler::subss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 449 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 450 | EmitUint8(0xF3); |
| 451 | EmitUint8(0x0F); |
| 452 | EmitUint8(0x5C); |
| 453 | EmitXmmRegisterOperand(dst, src); |
| 454 | } |
| 455 | |
| 456 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 457 | void X86Assembler::subss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 458 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 459 | EmitUint8(0xF3); |
| 460 | EmitUint8(0x0F); |
| 461 | EmitUint8(0x5C); |
| 462 | EmitOperand(dst, src); |
| 463 | } |
| 464 | |
| 465 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 466 | void X86Assembler::mulss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 467 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 468 | EmitUint8(0xF3); |
| 469 | EmitUint8(0x0F); |
| 470 | EmitUint8(0x59); |
| 471 | EmitXmmRegisterOperand(dst, src); |
| 472 | } |
| 473 | |
| 474 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 475 | void X86Assembler::mulss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 476 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 477 | EmitUint8(0xF3); |
| 478 | EmitUint8(0x0F); |
| 479 | EmitUint8(0x59); |
| 480 | EmitOperand(dst, src); |
| 481 | } |
| 482 | |
| 483 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 484 | void X86Assembler::divss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 485 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 486 | EmitUint8(0xF3); |
| 487 | EmitUint8(0x0F); |
| 488 | EmitUint8(0x5E); |
| 489 | EmitXmmRegisterOperand(dst, src); |
| 490 | } |
| 491 | |
| 492 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 493 | void X86Assembler::divss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 494 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 495 | EmitUint8(0xF3); |
| 496 | EmitUint8(0x0F); |
| 497 | EmitUint8(0x5E); |
| 498 | EmitOperand(dst, src); |
| 499 | } |
| 500 | |
| 501 | |
Aart Bik | c778226 | 2017-01-13 16:20:08 -0800 | [diff] [blame] | 502 | void X86Assembler::addps(XmmRegister dst, XmmRegister src) { |
| 503 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 504 | EmitUint8(0x0F); |
| 505 | EmitUint8(0x58); |
| 506 | EmitXmmRegisterOperand(dst, src); |
| 507 | } |
| 508 | |
| 509 | |
| 510 | void X86Assembler::subps(XmmRegister dst, XmmRegister src) { |
| 511 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 512 | EmitUint8(0x0F); |
| 513 | EmitUint8(0x5C); |
| 514 | EmitXmmRegisterOperand(dst, src); |
| 515 | } |
| 516 | |
| 517 | |
| 518 | void X86Assembler::mulps(XmmRegister dst, XmmRegister src) { |
| 519 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 520 | EmitUint8(0x0F); |
| 521 | EmitUint8(0x59); |
| 522 | EmitXmmRegisterOperand(dst, src); |
| 523 | } |
| 524 | |
| 525 | |
| 526 | void X86Assembler::divps(XmmRegister dst, XmmRegister src) { |
| 527 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 528 | EmitUint8(0x0F); |
| 529 | EmitUint8(0x5E); |
| 530 | EmitXmmRegisterOperand(dst, src); |
| 531 | } |
| 532 | |
| 533 | |
| 534 | void X86Assembler::movapd(XmmRegister dst, XmmRegister src) { |
| 535 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 536 | EmitUint8(0x66); |
| 537 | EmitUint8(0x0F); |
| 538 | EmitUint8(0x28); |
| 539 | EmitXmmRegisterOperand(dst, src); |
| 540 | } |
| 541 | |
| 542 | |
| 543 | void X86Assembler::movapd(XmmRegister dst, const Address& src) { |
| 544 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 545 | EmitUint8(0x66); |
| 546 | EmitUint8(0x0F); |
| 547 | EmitUint8(0x28); |
| 548 | EmitOperand(dst, src); |
| 549 | } |
| 550 | |
| 551 | |
| 552 | void X86Assembler::movupd(XmmRegister dst, const Address& src) { |
| 553 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 554 | EmitUint8(0x66); |
| 555 | EmitUint8(0x0F); |
| 556 | EmitUint8(0x10); |
| 557 | EmitOperand(dst, src); |
| 558 | } |
| 559 | |
| 560 | |
| 561 | void X86Assembler::movapd(const Address& dst, XmmRegister src) { |
| 562 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 563 | EmitUint8(0x66); |
| 564 | EmitUint8(0x0F); |
| 565 | EmitUint8(0x29); |
| 566 | EmitOperand(src, dst); |
| 567 | } |
| 568 | |
| 569 | |
| 570 | void X86Assembler::movupd(const Address& dst, XmmRegister src) { |
| 571 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 572 | EmitUint8(0x66); |
| 573 | EmitUint8(0x0F); |
| 574 | EmitUint8(0x11); |
| 575 | EmitOperand(src, dst); |
| 576 | } |
| 577 | |
| 578 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 579 | void X86Assembler::flds(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 580 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 581 | EmitUint8(0xD9); |
| 582 | EmitOperand(0, src); |
| 583 | } |
| 584 | |
| 585 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 586 | void X86Assembler::fsts(const Address& dst) { |
| 587 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 588 | EmitUint8(0xD9); |
| 589 | EmitOperand(2, dst); |
| 590 | } |
| 591 | |
| 592 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 593 | void X86Assembler::fstps(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 594 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 595 | EmitUint8(0xD9); |
| 596 | EmitOperand(3, dst); |
| 597 | } |
| 598 | |
| 599 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 600 | void X86Assembler::movsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 601 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 602 | EmitUint8(0xF2); |
| 603 | EmitUint8(0x0F); |
| 604 | EmitUint8(0x10); |
| 605 | EmitOperand(dst, src); |
| 606 | } |
| 607 | |
| 608 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 609 | void X86Assembler::movsd(const Address& dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 610 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 611 | EmitUint8(0xF2); |
| 612 | EmitUint8(0x0F); |
| 613 | EmitUint8(0x11); |
| 614 | EmitOperand(src, dst); |
| 615 | } |
| 616 | |
| 617 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 618 | void X86Assembler::movsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 619 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 620 | EmitUint8(0xF2); |
| 621 | EmitUint8(0x0F); |
| 622 | EmitUint8(0x11); |
| 623 | EmitXmmRegisterOperand(src, dst); |
| 624 | } |
| 625 | |
| 626 | |
Nicolas Geoffray | 234d69d | 2015-03-09 10:28:50 +0000 | [diff] [blame] | 627 | void X86Assembler::movhpd(XmmRegister dst, const Address& src) { |
| 628 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 629 | EmitUint8(0x66); |
| 630 | EmitUint8(0x0F); |
| 631 | EmitUint8(0x16); |
| 632 | EmitOperand(dst, src); |
| 633 | } |
| 634 | |
| 635 | |
| 636 | void X86Assembler::movhpd(const Address& dst, XmmRegister src) { |
| 637 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 638 | EmitUint8(0x66); |
| 639 | EmitUint8(0x0F); |
| 640 | EmitUint8(0x17); |
| 641 | EmitOperand(src, dst); |
| 642 | } |
| 643 | |
| 644 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 645 | void X86Assembler::addsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 646 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 647 | EmitUint8(0xF2); |
| 648 | EmitUint8(0x0F); |
| 649 | EmitUint8(0x58); |
| 650 | EmitXmmRegisterOperand(dst, src); |
| 651 | } |
| 652 | |
| 653 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 654 | void X86Assembler::addsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 655 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 656 | EmitUint8(0xF2); |
| 657 | EmitUint8(0x0F); |
| 658 | EmitUint8(0x58); |
| 659 | EmitOperand(dst, src); |
| 660 | } |
| 661 | |
| 662 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 663 | void X86Assembler::subsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 664 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 665 | EmitUint8(0xF2); |
| 666 | EmitUint8(0x0F); |
| 667 | EmitUint8(0x5C); |
| 668 | EmitXmmRegisterOperand(dst, src); |
| 669 | } |
| 670 | |
| 671 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 672 | void X86Assembler::subsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 673 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 674 | EmitUint8(0xF2); |
| 675 | EmitUint8(0x0F); |
| 676 | EmitUint8(0x5C); |
| 677 | EmitOperand(dst, src); |
| 678 | } |
| 679 | |
| 680 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 681 | void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 682 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 683 | EmitUint8(0xF2); |
| 684 | EmitUint8(0x0F); |
| 685 | EmitUint8(0x59); |
| 686 | EmitXmmRegisterOperand(dst, src); |
| 687 | } |
| 688 | |
| 689 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 690 | void X86Assembler::mulsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 691 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 692 | EmitUint8(0xF2); |
| 693 | EmitUint8(0x0F); |
| 694 | EmitUint8(0x59); |
| 695 | EmitOperand(dst, src); |
| 696 | } |
| 697 | |
| 698 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 699 | void X86Assembler::divsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 700 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 701 | EmitUint8(0xF2); |
| 702 | EmitUint8(0x0F); |
| 703 | EmitUint8(0x5E); |
| 704 | EmitXmmRegisterOperand(dst, src); |
| 705 | } |
| 706 | |
| 707 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 708 | void X86Assembler::divsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 709 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 710 | EmitUint8(0xF2); |
| 711 | EmitUint8(0x0F); |
| 712 | EmitUint8(0x5E); |
| 713 | EmitOperand(dst, src); |
| 714 | } |
| 715 | |
| 716 | |
Aart Bik | c778226 | 2017-01-13 16:20:08 -0800 | [diff] [blame] | 717 | void X86Assembler::addpd(XmmRegister dst, XmmRegister src) { |
| 718 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 719 | EmitUint8(0x66); |
| 720 | EmitUint8(0x0F); |
| 721 | EmitUint8(0x58); |
| 722 | EmitXmmRegisterOperand(dst, src); |
| 723 | } |
| 724 | |
| 725 | |
| 726 | void X86Assembler::subpd(XmmRegister dst, XmmRegister src) { |
| 727 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 728 | EmitUint8(0x66); |
| 729 | EmitUint8(0x0F); |
| 730 | EmitUint8(0x5C); |
| 731 | EmitXmmRegisterOperand(dst, src); |
| 732 | } |
| 733 | |
| 734 | |
| 735 | void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) { |
| 736 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 737 | EmitUint8(0x66); |
| 738 | EmitUint8(0x0F); |
| 739 | EmitUint8(0x59); |
| 740 | EmitXmmRegisterOperand(dst, src); |
| 741 | } |
| 742 | |
| 743 | |
| 744 | void X86Assembler::divpd(XmmRegister dst, XmmRegister src) { |
| 745 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 746 | EmitUint8(0x66); |
| 747 | EmitUint8(0x0F); |
| 748 | EmitUint8(0x5E); |
| 749 | EmitXmmRegisterOperand(dst, src); |
| 750 | } |
| 751 | |
| 752 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 753 | void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) { |
| 754 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 755 | EmitUint8(0x66); |
| 756 | EmitUint8(0x0F); |
| 757 | EmitUint8(0x6F); |
| 758 | EmitXmmRegisterOperand(dst, src); |
| 759 | } |
| 760 | |
| 761 | |
| 762 | void X86Assembler::movdqa(XmmRegister dst, const Address& src) { |
| 763 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 764 | EmitUint8(0x66); |
| 765 | EmitUint8(0x0F); |
| 766 | EmitUint8(0x6F); |
| 767 | EmitOperand(dst, src); |
| 768 | } |
| 769 | |
| 770 | |
| 771 | void X86Assembler::movdqu(XmmRegister dst, const Address& src) { |
| 772 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 773 | EmitUint8(0xF3); |
| 774 | EmitUint8(0x0F); |
| 775 | EmitUint8(0x6F); |
| 776 | EmitOperand(dst, src); |
| 777 | } |
| 778 | |
| 779 | |
| 780 | void X86Assembler::movdqa(const Address& dst, XmmRegister src) { |
| 781 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 782 | EmitUint8(0x66); |
| 783 | EmitUint8(0x0F); |
| 784 | EmitUint8(0x7F); |
| 785 | EmitOperand(src, dst); |
| 786 | } |
| 787 | |
| 788 | |
| 789 | void X86Assembler::movdqu(const Address& dst, XmmRegister src) { |
| 790 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 791 | EmitUint8(0xF3); |
| 792 | EmitUint8(0x0F); |
| 793 | EmitUint8(0x7F); |
| 794 | EmitOperand(src, dst); |
| 795 | } |
| 796 | |
| 797 | |
Aart Bik | e69d7a9 | 2017-02-17 11:48:23 -0800 | [diff] [blame^] | 798 | void X86Assembler::paddb(XmmRegister dst, XmmRegister src) { |
| 799 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 800 | EmitUint8(0x66); |
| 801 | EmitUint8(0x0F); |
| 802 | EmitUint8(0xFC); |
| 803 | EmitXmmRegisterOperand(dst, src); |
| 804 | } |
| 805 | |
| 806 | |
| 807 | void X86Assembler::psubb(XmmRegister dst, XmmRegister src) { |
| 808 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 809 | EmitUint8(0x66); |
| 810 | EmitUint8(0x0F); |
| 811 | EmitUint8(0xF8); |
| 812 | EmitXmmRegisterOperand(dst, src); |
| 813 | } |
| 814 | |
| 815 | |
| 816 | void X86Assembler::paddw(XmmRegister dst, XmmRegister src) { |
| 817 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 818 | EmitUint8(0x66); |
| 819 | EmitUint8(0x0F); |
| 820 | EmitUint8(0xFD); |
| 821 | EmitXmmRegisterOperand(dst, src); |
| 822 | } |
| 823 | |
| 824 | |
| 825 | void X86Assembler::psubw(XmmRegister dst, XmmRegister src) { |
| 826 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 827 | EmitUint8(0x66); |
| 828 | EmitUint8(0x0F); |
| 829 | EmitUint8(0xF9); |
| 830 | EmitXmmRegisterOperand(dst, src); |
| 831 | } |
| 832 | |
| 833 | |
| 834 | void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) { |
| 835 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 836 | EmitUint8(0x66); |
| 837 | EmitUint8(0x0F); |
| 838 | EmitUint8(0xD5); |
| 839 | EmitXmmRegisterOperand(dst, src); |
| 840 | } |
| 841 | |
| 842 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 843 | void X86Assembler::paddd(XmmRegister dst, XmmRegister src) { |
| 844 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 845 | EmitUint8(0x66); |
| 846 | EmitUint8(0x0F); |
| 847 | EmitUint8(0xFE); |
| 848 | EmitXmmRegisterOperand(dst, src); |
| 849 | } |
| 850 | |
| 851 | |
| 852 | void X86Assembler::psubd(XmmRegister dst, XmmRegister src) { |
| 853 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 854 | EmitUint8(0x66); |
| 855 | EmitUint8(0x0F); |
| 856 | EmitUint8(0xFA); |
| 857 | EmitXmmRegisterOperand(dst, src); |
| 858 | } |
| 859 | |
| 860 | |
| 861 | void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) { |
| 862 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 863 | EmitUint8(0x66); |
| 864 | EmitUint8(0x0F); |
| 865 | EmitUint8(0x38); |
| 866 | EmitUint8(0x40); |
| 867 | EmitXmmRegisterOperand(dst, src); |
| 868 | } |
| 869 | |
| 870 | |
Aart Bik | e69d7a9 | 2017-02-17 11:48:23 -0800 | [diff] [blame^] | 871 | void X86Assembler::paddq(XmmRegister dst, XmmRegister src) { |
| 872 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 873 | EmitUint8(0x66); |
| 874 | EmitUint8(0x0F); |
| 875 | EmitUint8(0xD4); |
| 876 | EmitXmmRegisterOperand(dst, src); |
| 877 | } |
| 878 | |
| 879 | |
| 880 | void X86Assembler::psubq(XmmRegister dst, XmmRegister src) { |
| 881 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 882 | EmitUint8(0x66); |
| 883 | EmitUint8(0x0F); |
| 884 | EmitUint8(0xFB); |
| 885 | EmitXmmRegisterOperand(dst, src); |
| 886 | } |
| 887 | |
| 888 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 889 | void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 890 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 891 | EmitUint8(0xF3); |
| 892 | EmitUint8(0x0F); |
| 893 | EmitUint8(0x2A); |
| 894 | EmitOperand(dst, Operand(src)); |
| 895 | } |
| 896 | |
| 897 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 898 | void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 899 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 900 | EmitUint8(0xF2); |
| 901 | EmitUint8(0x0F); |
| 902 | EmitUint8(0x2A); |
| 903 | EmitOperand(dst, Operand(src)); |
| 904 | } |
| 905 | |
| 906 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 907 | void X86Assembler::cvtss2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 908 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 909 | EmitUint8(0xF3); |
| 910 | EmitUint8(0x0F); |
| 911 | EmitUint8(0x2D); |
| 912 | EmitXmmRegisterOperand(dst, src); |
| 913 | } |
| 914 | |
| 915 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 916 | void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 917 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 918 | EmitUint8(0xF3); |
| 919 | EmitUint8(0x0F); |
| 920 | EmitUint8(0x5A); |
| 921 | EmitXmmRegisterOperand(dst, src); |
| 922 | } |
| 923 | |
| 924 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 925 | void X86Assembler::cvtsd2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 926 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 927 | EmitUint8(0xF2); |
| 928 | EmitUint8(0x0F); |
| 929 | EmitUint8(0x2D); |
| 930 | EmitXmmRegisterOperand(dst, src); |
| 931 | } |
| 932 | |
| 933 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 934 | void X86Assembler::cvttss2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 935 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 936 | EmitUint8(0xF3); |
| 937 | EmitUint8(0x0F); |
| 938 | EmitUint8(0x2C); |
| 939 | EmitXmmRegisterOperand(dst, src); |
| 940 | } |
| 941 | |
| 942 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 943 | void X86Assembler::cvttsd2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 944 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 945 | EmitUint8(0xF2); |
| 946 | EmitUint8(0x0F); |
| 947 | EmitUint8(0x2C); |
| 948 | EmitXmmRegisterOperand(dst, src); |
| 949 | } |
| 950 | |
| 951 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 952 | void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 953 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 954 | EmitUint8(0xF2); |
| 955 | EmitUint8(0x0F); |
| 956 | EmitUint8(0x5A); |
| 957 | EmitXmmRegisterOperand(dst, src); |
| 958 | } |
| 959 | |
| 960 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 961 | void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 962 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 963 | EmitUint8(0xF3); |
| 964 | EmitUint8(0x0F); |
| 965 | EmitUint8(0xE6); |
| 966 | EmitXmmRegisterOperand(dst, src); |
| 967 | } |
| 968 | |
| 969 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 970 | void X86Assembler::comiss(XmmRegister a, XmmRegister b) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 971 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 972 | EmitUint8(0x0F); |
| 973 | EmitUint8(0x2F); |
| 974 | EmitXmmRegisterOperand(a, b); |
| 975 | } |
| 976 | |
| 977 | |
Aart Bik | 18ba121 | 2016-08-01 14:11:20 -0700 | [diff] [blame] | 978 | void X86Assembler::comiss(XmmRegister a, const Address& b) { |
| 979 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 980 | EmitUint8(0x0F); |
| 981 | EmitUint8(0x2F); |
| 982 | EmitOperand(a, b); |
| 983 | } |
| 984 | |
| 985 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 986 | void X86Assembler::comisd(XmmRegister a, XmmRegister b) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 987 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 988 | EmitUint8(0x66); |
| 989 | EmitUint8(0x0F); |
| 990 | EmitUint8(0x2F); |
| 991 | EmitXmmRegisterOperand(a, b); |
| 992 | } |
| 993 | |
| 994 | |
Aart Bik | 18ba121 | 2016-08-01 14:11:20 -0700 | [diff] [blame] | 995 | void X86Assembler::comisd(XmmRegister a, const Address& b) { |
| 996 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 997 | EmitUint8(0x66); |
| 998 | EmitUint8(0x0F); |
| 999 | EmitUint8(0x2F); |
| 1000 | EmitOperand(a, b); |
| 1001 | } |
| 1002 | |
| 1003 | |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 1004 | void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) { |
| 1005 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1006 | EmitUint8(0x0F); |
| 1007 | EmitUint8(0x2E); |
| 1008 | EmitXmmRegisterOperand(a, b); |
| 1009 | } |
| 1010 | |
| 1011 | |
Mark Mendell | 9f51f26 | 2015-10-30 09:21:37 -0400 | [diff] [blame] | 1012 | void X86Assembler::ucomiss(XmmRegister a, const Address& b) { |
| 1013 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1014 | EmitUint8(0x0F); |
| 1015 | EmitUint8(0x2E); |
| 1016 | EmitOperand(a, b); |
| 1017 | } |
| 1018 | |
| 1019 | |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 1020 | void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) { |
| 1021 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1022 | EmitUint8(0x66); |
| 1023 | EmitUint8(0x0F); |
| 1024 | EmitUint8(0x2E); |
| 1025 | EmitXmmRegisterOperand(a, b); |
| 1026 | } |
| 1027 | |
| 1028 | |
Mark Mendell | 9f51f26 | 2015-10-30 09:21:37 -0400 | [diff] [blame] | 1029 | void X86Assembler::ucomisd(XmmRegister a, const Address& b) { |
| 1030 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1031 | EmitUint8(0x66); |
| 1032 | EmitUint8(0x0F); |
| 1033 | EmitUint8(0x2E); |
| 1034 | EmitOperand(a, b); |
| 1035 | } |
| 1036 | |
| 1037 | |
Mark Mendell | fb8d279 | 2015-03-31 22:16:59 -0400 | [diff] [blame] | 1038 | void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 1039 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1040 | EmitUint8(0x66); |
| 1041 | EmitUint8(0x0F); |
| 1042 | EmitUint8(0x3A); |
| 1043 | EmitUint8(0x0B); |
| 1044 | EmitXmmRegisterOperand(dst, src); |
| 1045 | EmitUint8(imm.value()); |
| 1046 | } |
| 1047 | |
| 1048 | |
| 1049 | void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 1050 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1051 | EmitUint8(0x66); |
| 1052 | EmitUint8(0x0F); |
| 1053 | EmitUint8(0x3A); |
| 1054 | EmitUint8(0x0A); |
| 1055 | EmitXmmRegisterOperand(dst, src); |
| 1056 | EmitUint8(imm.value()); |
| 1057 | } |
| 1058 | |
| 1059 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1060 | void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1061 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1062 | EmitUint8(0xF2); |
| 1063 | EmitUint8(0x0F); |
| 1064 | EmitUint8(0x51); |
| 1065 | EmitXmmRegisterOperand(dst, src); |
| 1066 | } |
| 1067 | |
| 1068 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1069 | void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1070 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1071 | EmitUint8(0xF3); |
| 1072 | EmitUint8(0x0F); |
| 1073 | EmitUint8(0x51); |
| 1074 | EmitXmmRegisterOperand(dst, src); |
| 1075 | } |
| 1076 | |
| 1077 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1078 | void X86Assembler::xorpd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1079 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1080 | EmitUint8(0x66); |
| 1081 | EmitUint8(0x0F); |
| 1082 | EmitUint8(0x57); |
| 1083 | EmitOperand(dst, src); |
| 1084 | } |
| 1085 | |
| 1086 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1087 | void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1088 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1089 | EmitUint8(0x66); |
| 1090 | EmitUint8(0x0F); |
| 1091 | EmitUint8(0x57); |
| 1092 | EmitXmmRegisterOperand(dst, src); |
| 1093 | } |
| 1094 | |
| 1095 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1096 | void X86Assembler::xorps(XmmRegister dst, const Address& src) { |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1097 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1098 | EmitUint8(0x0F); |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1099 | EmitUint8(0x57); |
| 1100 | EmitOperand(dst, src); |
| 1101 | } |
| 1102 | |
| 1103 | |
| 1104 | void X86Assembler::xorps(XmmRegister dst, XmmRegister src) { |
| 1105 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1106 | EmitUint8(0x0F); |
| 1107 | EmitUint8(0x57); |
| 1108 | EmitXmmRegisterOperand(dst, src); |
| 1109 | } |
| 1110 | |
| 1111 | |
| 1112 | void X86Assembler::pxor(XmmRegister dst, XmmRegister src) { |
| 1113 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1114 | EmitUint8(0x66); |
| 1115 | EmitUint8(0x0F); |
| 1116 | EmitUint8(0xEF); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1117 | EmitXmmRegisterOperand(dst, src); |
| 1118 | } |
| 1119 | |
| 1120 | |
| 1121 | void X86Assembler::andpd(XmmRegister dst, XmmRegister src) { |
| 1122 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1123 | EmitUint8(0x66); |
| 1124 | EmitUint8(0x0F); |
| 1125 | EmitUint8(0x54); |
| 1126 | EmitXmmRegisterOperand(dst, src); |
| 1127 | } |
| 1128 | |
| 1129 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1130 | void X86Assembler::andpd(XmmRegister dst, const Address& src) { |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1131 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1132 | EmitUint8(0x66); |
| 1133 | EmitUint8(0x0F); |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1134 | EmitUint8(0x54); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1135 | EmitOperand(dst, src); |
| 1136 | } |
| 1137 | |
| 1138 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1139 | void X86Assembler::andps(XmmRegister dst, XmmRegister src) { |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1140 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1141 | EmitUint8(0x0F); |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1142 | EmitUint8(0x54); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1143 | EmitXmmRegisterOperand(dst, src); |
| 1144 | } |
| 1145 | |
| 1146 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1147 | void X86Assembler::andps(XmmRegister dst, const Address& src) { |
| 1148 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1149 | EmitUint8(0x0F); |
| 1150 | EmitUint8(0x54); |
| 1151 | EmitOperand(dst, src); |
| 1152 | } |
| 1153 | |
| 1154 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1155 | void X86Assembler::pand(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1156 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1157 | EmitUint8(0x66); |
| 1158 | EmitUint8(0x0F); |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1159 | EmitUint8(0xDB); |
| 1160 | EmitXmmRegisterOperand(dst, src); |
| 1161 | } |
| 1162 | |
| 1163 | |
| 1164 | void X86Assembler::orpd(XmmRegister dst, XmmRegister src) { |
| 1165 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1166 | EmitUint8(0x66); |
| 1167 | EmitUint8(0x0F); |
| 1168 | EmitUint8(0x56); |
| 1169 | EmitXmmRegisterOperand(dst, src); |
| 1170 | } |
| 1171 | |
| 1172 | |
| 1173 | void X86Assembler::orps(XmmRegister dst, XmmRegister src) { |
| 1174 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1175 | EmitUint8(0x0F); |
| 1176 | EmitUint8(0x56); |
| 1177 | EmitXmmRegisterOperand(dst, src); |
| 1178 | } |
| 1179 | |
| 1180 | |
| 1181 | void X86Assembler::por(XmmRegister dst, XmmRegister src) { |
| 1182 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1183 | EmitUint8(0x66); |
| 1184 | EmitUint8(0x0F); |
| 1185 | EmitUint8(0xEB); |
| 1186 | EmitXmmRegisterOperand(dst, src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1187 | } |
| 1188 | |
| 1189 | |
Aart Bik | 12e06ed | 2017-01-31 16:11:24 -0800 | [diff] [blame] | 1190 | void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 1191 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1192 | EmitUint8(0x66); |
| 1193 | EmitUint8(0x0F); |
| 1194 | EmitUint8(0xC6); |
| 1195 | EmitXmmRegisterOperand(dst, src); |
| 1196 | EmitUint8(imm.value()); |
| 1197 | } |
| 1198 | |
| 1199 | |
| 1200 | void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 1201 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1202 | EmitUint8(0x0F); |
| 1203 | EmitUint8(0xC6); |
| 1204 | EmitXmmRegisterOperand(dst, src); |
| 1205 | EmitUint8(imm.value()); |
| 1206 | } |
| 1207 | |
| 1208 | |
Aart Bik | 68555e9 | 2017-02-13 14:28:45 -0800 | [diff] [blame] | 1209 | void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 1210 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1211 | EmitUint8(0x66); |
| 1212 | EmitUint8(0x0F); |
| 1213 | EmitUint8(0x70); |
| 1214 | EmitXmmRegisterOperand(dst, src); |
| 1215 | EmitUint8(imm.value()); |
| 1216 | } |
| 1217 | |
| 1218 | |
Aart Bik | e69d7a9 | 2017-02-17 11:48:23 -0800 | [diff] [blame^] | 1219 | void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) { |
| 1220 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1221 | EmitUint8(0x66); |
| 1222 | EmitUint8(0x0F); |
| 1223 | EmitUint8(0x60); |
| 1224 | EmitXmmRegisterOperand(dst, src); |
| 1225 | } |
| 1226 | |
| 1227 | |
| 1228 | void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) { |
| 1229 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1230 | EmitUint8(0x66); |
| 1231 | EmitUint8(0x0F); |
| 1232 | EmitUint8(0x61); |
| 1233 | EmitXmmRegisterOperand(dst, src); |
| 1234 | } |
| 1235 | |
| 1236 | |
| 1237 | void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) { |
| 1238 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1239 | EmitUint8(0x66); |
| 1240 | EmitUint8(0x0F); |
| 1241 | EmitUint8(0x62); |
| 1242 | EmitXmmRegisterOperand(dst, src); |
| 1243 | } |
| 1244 | |
| 1245 | |
| 1246 | void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) { |
| 1247 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1248 | EmitUint8(0x66); |
| 1249 | EmitUint8(0x0F); |
| 1250 | EmitUint8(0x6C); |
| 1251 | EmitXmmRegisterOperand(dst, src); |
| 1252 | } |
| 1253 | |
| 1254 | |
| 1255 | void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) { |
| 1256 | DCHECK(shift_count.is_uint8()); |
| 1257 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1258 | EmitUint8(0x66); |
| 1259 | EmitUint8(0x0F); |
| 1260 | EmitUint8(0x71); |
| 1261 | EmitXmmRegisterOperand(6, reg); |
| 1262 | EmitUint8(shift_count.value()); |
| 1263 | } |
| 1264 | |
| 1265 | |
| 1266 | void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) { |
| 1267 | DCHECK(shift_count.is_uint8()); |
| 1268 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1269 | EmitUint8(0x66); |
| 1270 | EmitUint8(0x0F); |
| 1271 | EmitUint8(0x72); |
| 1272 | EmitXmmRegisterOperand(6, reg); |
| 1273 | EmitUint8(shift_count.value()); |
| 1274 | } |
| 1275 | |
| 1276 | |
| 1277 | void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) { |
| 1278 | DCHECK(shift_count.is_uint8()); |
| 1279 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1280 | EmitUint8(0x66); |
| 1281 | EmitUint8(0x0F); |
| 1282 | EmitUint8(0x73); |
| 1283 | EmitXmmRegisterOperand(6, reg); |
| 1284 | EmitUint8(shift_count.value()); |
| 1285 | } |
| 1286 | |
| 1287 | |
| 1288 | void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) { |
| 1289 | DCHECK(shift_count.is_uint8()); |
| 1290 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1291 | EmitUint8(0x66); |
| 1292 | EmitUint8(0x0F); |
| 1293 | EmitUint8(0x71); |
| 1294 | EmitXmmRegisterOperand(4, reg); |
| 1295 | EmitUint8(shift_count.value()); |
| 1296 | } |
| 1297 | |
| 1298 | |
| 1299 | void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) { |
| 1300 | DCHECK(shift_count.is_uint8()); |
| 1301 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1302 | EmitUint8(0x66); |
| 1303 | EmitUint8(0x0F); |
| 1304 | EmitUint8(0x72); |
| 1305 | EmitXmmRegisterOperand(4, reg); |
| 1306 | EmitUint8(shift_count.value()); |
| 1307 | } |
| 1308 | |
| 1309 | |
| 1310 | void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) { |
| 1311 | DCHECK(shift_count.is_uint8()); |
| 1312 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1313 | EmitUint8(0x66); |
| 1314 | EmitUint8(0x0F); |
| 1315 | EmitUint8(0x71); |
| 1316 | EmitXmmRegisterOperand(2, reg); |
| 1317 | EmitUint8(shift_count.value()); |
| 1318 | } |
| 1319 | |
| 1320 | |
| 1321 | void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) { |
| 1322 | DCHECK(shift_count.is_uint8()); |
| 1323 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1324 | EmitUint8(0x66); |
| 1325 | EmitUint8(0x0F); |
| 1326 | EmitUint8(0x72); |
| 1327 | EmitXmmRegisterOperand(2, reg); |
| 1328 | EmitUint8(shift_count.value()); |
| 1329 | } |
| 1330 | |
| 1331 | |
| 1332 | void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) { |
| 1333 | DCHECK(shift_count.is_uint8()); |
| 1334 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1335 | EmitUint8(0x66); |
| 1336 | EmitUint8(0x0F); |
| 1337 | EmitUint8(0x73); |
| 1338 | EmitXmmRegisterOperand(2, reg); |
| 1339 | EmitUint8(shift_count.value()); |
| 1340 | } |
| 1341 | |
| 1342 | |
| 1343 | void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) { |
| 1344 | DCHECK(shift_count.is_uint8()); |
| 1345 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1346 | EmitUint8(0x66); |
| 1347 | EmitUint8(0x0F); |
| 1348 | EmitUint8(0x73); |
| 1349 | EmitXmmRegisterOperand(3, reg); |
| 1350 | EmitUint8(shift_count.value()); |
| 1351 | } |
| 1352 | |
| 1353 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1354 | void X86Assembler::fldl(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1355 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1356 | EmitUint8(0xDD); |
| 1357 | EmitOperand(0, src); |
| 1358 | } |
| 1359 | |
| 1360 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1361 | void X86Assembler::fstl(const Address& dst) { |
| 1362 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1363 | EmitUint8(0xDD); |
| 1364 | EmitOperand(2, dst); |
| 1365 | } |
| 1366 | |
| 1367 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1368 | void X86Assembler::fstpl(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1369 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1370 | EmitUint8(0xDD); |
| 1371 | EmitOperand(3, dst); |
| 1372 | } |
| 1373 | |
| 1374 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1375 | void X86Assembler::fstsw() { |
| 1376 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1377 | EmitUint8(0x9B); |
| 1378 | EmitUint8(0xDF); |
| 1379 | EmitUint8(0xE0); |
| 1380 | } |
| 1381 | |
| 1382 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1383 | void X86Assembler::fnstcw(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1384 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1385 | EmitUint8(0xD9); |
| 1386 | EmitOperand(7, dst); |
| 1387 | } |
| 1388 | |
| 1389 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1390 | void X86Assembler::fldcw(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1391 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1392 | EmitUint8(0xD9); |
| 1393 | EmitOperand(5, src); |
| 1394 | } |
| 1395 | |
| 1396 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1397 | void X86Assembler::fistpl(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1398 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1399 | EmitUint8(0xDF); |
| 1400 | EmitOperand(7, dst); |
| 1401 | } |
| 1402 | |
| 1403 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1404 | void X86Assembler::fistps(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1405 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1406 | EmitUint8(0xDB); |
| 1407 | EmitOperand(3, dst); |
| 1408 | } |
| 1409 | |
| 1410 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1411 | void X86Assembler::fildl(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1412 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1413 | EmitUint8(0xDF); |
| 1414 | EmitOperand(5, src); |
| 1415 | } |
| 1416 | |
| 1417 | |
Roland Levillain | 0a18601 | 2015-04-13 17:00:20 +0100 | [diff] [blame] | 1418 | void X86Assembler::filds(const Address& src) { |
| 1419 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1420 | EmitUint8(0xDB); |
| 1421 | EmitOperand(0, src); |
| 1422 | } |
| 1423 | |
| 1424 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1425 | void X86Assembler::fincstp() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1426 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1427 | EmitUint8(0xD9); |
| 1428 | EmitUint8(0xF7); |
| 1429 | } |
| 1430 | |
| 1431 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1432 | void X86Assembler::ffree(const Immediate& index) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1433 | CHECK_LT(index.value(), 7); |
| 1434 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1435 | EmitUint8(0xDD); |
| 1436 | EmitUint8(0xC0 + index.value()); |
| 1437 | } |
| 1438 | |
| 1439 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1440 | void X86Assembler::fsin() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1441 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1442 | EmitUint8(0xD9); |
| 1443 | EmitUint8(0xFE); |
| 1444 | } |
| 1445 | |
| 1446 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1447 | void X86Assembler::fcos() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1448 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1449 | EmitUint8(0xD9); |
| 1450 | EmitUint8(0xFF); |
| 1451 | } |
| 1452 | |
| 1453 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1454 | void X86Assembler::fptan() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1455 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1456 | EmitUint8(0xD9); |
| 1457 | EmitUint8(0xF2); |
| 1458 | } |
| 1459 | |
| 1460 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1461 | void X86Assembler::fucompp() { |
| 1462 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1463 | EmitUint8(0xDA); |
| 1464 | EmitUint8(0xE9); |
| 1465 | } |
| 1466 | |
| 1467 | |
| 1468 | void X86Assembler::fprem() { |
| 1469 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1470 | EmitUint8(0xD9); |
| 1471 | EmitUint8(0xF8); |
| 1472 | } |
| 1473 | |
| 1474 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1475 | void X86Assembler::xchgl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1476 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1477 | EmitUint8(0x87); |
| 1478 | EmitRegisterOperand(dst, src); |
| 1479 | } |
| 1480 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 1481 | |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 1482 | void X86Assembler::xchgl(Register reg, const Address& address) { |
| 1483 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1484 | EmitUint8(0x87); |
| 1485 | EmitOperand(reg, address); |
| 1486 | } |
| 1487 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1488 | |
Serguei Katkov | 3b62593 | 2016-05-06 10:24:17 +0600 | [diff] [blame] | 1489 | void X86Assembler::cmpb(const Address& address, const Immediate& imm) { |
| 1490 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1491 | EmitUint8(0x80); |
| 1492 | EmitOperand(7, address); |
| 1493 | EmitUint8(imm.value() & 0xFF); |
| 1494 | } |
| 1495 | |
| 1496 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 1497 | void X86Assembler::cmpw(const Address& address, const Immediate& imm) { |
| 1498 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1499 | EmitUint8(0x66); |
| 1500 | EmitComplex(7, address, imm); |
| 1501 | } |
| 1502 | |
| 1503 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1504 | void X86Assembler::cmpl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1505 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1506 | EmitComplex(7, Operand(reg), imm); |
| 1507 | } |
| 1508 | |
| 1509 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1510 | void X86Assembler::cmpl(Register reg0, Register reg1) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1511 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1512 | EmitUint8(0x3B); |
| 1513 | EmitOperand(reg0, Operand(reg1)); |
| 1514 | } |
| 1515 | |
| 1516 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1517 | void X86Assembler::cmpl(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1518 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1519 | EmitUint8(0x3B); |
| 1520 | EmitOperand(reg, address); |
| 1521 | } |
| 1522 | |
| 1523 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1524 | void X86Assembler::addl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1525 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1526 | EmitUint8(0x03); |
| 1527 | EmitRegisterOperand(dst, src); |
| 1528 | } |
| 1529 | |
| 1530 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1531 | void X86Assembler::addl(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1532 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1533 | EmitUint8(0x03); |
| 1534 | EmitOperand(reg, address); |
| 1535 | } |
| 1536 | |
| 1537 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1538 | void X86Assembler::cmpl(const Address& address, Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1539 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1540 | EmitUint8(0x39); |
| 1541 | EmitOperand(reg, address); |
| 1542 | } |
| 1543 | |
| 1544 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1545 | void X86Assembler::cmpl(const Address& address, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1546 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1547 | EmitComplex(7, address, imm); |
| 1548 | } |
| 1549 | |
| 1550 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1551 | void X86Assembler::testl(Register reg1, Register reg2) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1552 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1553 | EmitUint8(0x85); |
| 1554 | EmitRegisterOperand(reg1, reg2); |
| 1555 | } |
| 1556 | |
| 1557 | |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 1558 | void X86Assembler::testl(Register reg, const Address& address) { |
| 1559 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1560 | EmitUint8(0x85); |
| 1561 | EmitOperand(reg, address); |
| 1562 | } |
| 1563 | |
| 1564 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1565 | void X86Assembler::testl(Register reg, const Immediate& immediate) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1566 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1567 | // For registers that have a byte variant (EAX, EBX, ECX, and EDX) |
| 1568 | // we only test the byte register to keep the encoding short. |
| 1569 | if (immediate.is_uint8() && reg < 4) { |
| 1570 | // Use zero-extended 8-bit immediate. |
| 1571 | if (reg == EAX) { |
| 1572 | EmitUint8(0xA8); |
| 1573 | } else { |
| 1574 | EmitUint8(0xF6); |
| 1575 | EmitUint8(0xC0 + reg); |
| 1576 | } |
| 1577 | EmitUint8(immediate.value() & 0xFF); |
| 1578 | } else if (reg == EAX) { |
| 1579 | // Use short form if the destination is EAX. |
| 1580 | EmitUint8(0xA9); |
| 1581 | EmitImmediate(immediate); |
| 1582 | } else { |
| 1583 | EmitUint8(0xF7); |
| 1584 | EmitOperand(0, Operand(reg)); |
| 1585 | EmitImmediate(immediate); |
| 1586 | } |
| 1587 | } |
| 1588 | |
| 1589 | |
Vladimir Marko | 953437b | 2016-08-24 08:30:46 +0000 | [diff] [blame] | 1590 | void X86Assembler::testb(const Address& dst, const Immediate& imm) { |
| 1591 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1592 | EmitUint8(0xF6); |
| 1593 | EmitOperand(EAX, dst); |
| 1594 | CHECK(imm.is_int8()); |
| 1595 | EmitUint8(imm.value() & 0xFF); |
| 1596 | } |
| 1597 | |
| 1598 | |
| 1599 | void X86Assembler::testl(const Address& dst, const Immediate& imm) { |
| 1600 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1601 | EmitUint8(0xF7); |
| 1602 | EmitOperand(0, dst); |
| 1603 | EmitImmediate(imm); |
| 1604 | } |
| 1605 | |
| 1606 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1607 | void X86Assembler::andl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1608 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1609 | EmitUint8(0x23); |
| 1610 | EmitOperand(dst, Operand(src)); |
| 1611 | } |
| 1612 | |
| 1613 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1614 | void X86Assembler::andl(Register reg, const Address& address) { |
| 1615 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1616 | EmitUint8(0x23); |
| 1617 | EmitOperand(reg, address); |
| 1618 | } |
| 1619 | |
| 1620 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1621 | void X86Assembler::andl(Register dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1622 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1623 | EmitComplex(4, Operand(dst), imm); |
| 1624 | } |
| 1625 | |
| 1626 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1627 | void X86Assembler::orl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1628 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1629 | EmitUint8(0x0B); |
| 1630 | EmitOperand(dst, Operand(src)); |
| 1631 | } |
| 1632 | |
| 1633 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1634 | void X86Assembler::orl(Register reg, const Address& address) { |
| 1635 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1636 | EmitUint8(0x0B); |
| 1637 | EmitOperand(reg, address); |
| 1638 | } |
| 1639 | |
| 1640 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1641 | void X86Assembler::orl(Register dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1642 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1643 | EmitComplex(1, Operand(dst), imm); |
| 1644 | } |
| 1645 | |
| 1646 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1647 | void X86Assembler::xorl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1648 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1649 | EmitUint8(0x33); |
| 1650 | EmitOperand(dst, Operand(src)); |
| 1651 | } |
| 1652 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1653 | |
| 1654 | void X86Assembler::xorl(Register reg, const Address& address) { |
| 1655 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1656 | EmitUint8(0x33); |
| 1657 | EmitOperand(reg, address); |
| 1658 | } |
| 1659 | |
| 1660 | |
Nicolas Geoffray | b55f835 | 2014-04-07 15:26:35 +0100 | [diff] [blame] | 1661 | void X86Assembler::xorl(Register dst, const Immediate& imm) { |
| 1662 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1663 | EmitComplex(6, Operand(dst), imm); |
| 1664 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1665 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1666 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1667 | void X86Assembler::addl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1668 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1669 | EmitComplex(0, Operand(reg), imm); |
| 1670 | } |
| 1671 | |
| 1672 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1673 | void X86Assembler::addl(const Address& address, Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1674 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1675 | EmitUint8(0x01); |
| 1676 | EmitOperand(reg, address); |
| 1677 | } |
| 1678 | |
| 1679 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1680 | void X86Assembler::addl(const Address& address, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1681 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1682 | EmitComplex(0, address, imm); |
| 1683 | } |
| 1684 | |
| 1685 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1686 | void X86Assembler::adcl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1687 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1688 | EmitComplex(2, Operand(reg), imm); |
| 1689 | } |
| 1690 | |
| 1691 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1692 | void X86Assembler::adcl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1693 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1694 | EmitUint8(0x13); |
| 1695 | EmitOperand(dst, Operand(src)); |
| 1696 | } |
| 1697 | |
| 1698 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1699 | void X86Assembler::adcl(Register dst, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1700 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1701 | EmitUint8(0x13); |
| 1702 | EmitOperand(dst, address); |
| 1703 | } |
| 1704 | |
| 1705 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1706 | void X86Assembler::subl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1707 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1708 | EmitUint8(0x2B); |
| 1709 | EmitOperand(dst, Operand(src)); |
| 1710 | } |
| 1711 | |
| 1712 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1713 | void X86Assembler::subl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1714 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1715 | EmitComplex(5, Operand(reg), imm); |
| 1716 | } |
| 1717 | |
| 1718 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1719 | void X86Assembler::subl(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1720 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1721 | EmitUint8(0x2B); |
| 1722 | EmitOperand(reg, address); |
| 1723 | } |
| 1724 | |
| 1725 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1726 | void X86Assembler::subl(const Address& address, Register reg) { |
| 1727 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1728 | EmitUint8(0x29); |
| 1729 | EmitOperand(reg, address); |
| 1730 | } |
| 1731 | |
| 1732 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1733 | void X86Assembler::cdq() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1734 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1735 | EmitUint8(0x99); |
| 1736 | } |
| 1737 | |
| 1738 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1739 | void X86Assembler::idivl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1740 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1741 | EmitUint8(0xF7); |
| 1742 | EmitUint8(0xF8 | reg); |
| 1743 | } |
| 1744 | |
| 1745 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1746 | void X86Assembler::imull(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1747 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1748 | EmitUint8(0x0F); |
| 1749 | EmitUint8(0xAF); |
| 1750 | EmitOperand(dst, Operand(src)); |
| 1751 | } |
| 1752 | |
| 1753 | |
Mark Mendell | 4a2aa4a | 2015-07-27 16:13:10 -0400 | [diff] [blame] | 1754 | void X86Assembler::imull(Register dst, Register src, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1755 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 4a2aa4a | 2015-07-27 16:13:10 -0400 | [diff] [blame] | 1756 | // See whether imm can be represented as a sign-extended 8bit value. |
| 1757 | int32_t v32 = static_cast<int32_t>(imm.value()); |
| 1758 | if (IsInt<8>(v32)) { |
| 1759 | // Sign-extension works. |
| 1760 | EmitUint8(0x6B); |
| 1761 | EmitOperand(dst, Operand(src)); |
| 1762 | EmitUint8(static_cast<uint8_t>(v32 & 0xFF)); |
| 1763 | } else { |
| 1764 | // Not representable, use full immediate. |
| 1765 | EmitUint8(0x69); |
| 1766 | EmitOperand(dst, Operand(src)); |
| 1767 | EmitImmediate(imm); |
| 1768 | } |
| 1769 | } |
| 1770 | |
| 1771 | |
| 1772 | void X86Assembler::imull(Register reg, const Immediate& imm) { |
| 1773 | imull(reg, reg, imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1774 | } |
| 1775 | |
| 1776 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1777 | void X86Assembler::imull(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1778 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1779 | EmitUint8(0x0F); |
| 1780 | EmitUint8(0xAF); |
| 1781 | EmitOperand(reg, address); |
| 1782 | } |
| 1783 | |
| 1784 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1785 | void X86Assembler::imull(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1786 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1787 | EmitUint8(0xF7); |
| 1788 | EmitOperand(5, Operand(reg)); |
| 1789 | } |
| 1790 | |
| 1791 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1792 | void X86Assembler::imull(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1793 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1794 | EmitUint8(0xF7); |
| 1795 | EmitOperand(5, address); |
| 1796 | } |
| 1797 | |
| 1798 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1799 | void X86Assembler::mull(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1800 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1801 | EmitUint8(0xF7); |
| 1802 | EmitOperand(4, Operand(reg)); |
| 1803 | } |
| 1804 | |
| 1805 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1806 | void X86Assembler::mull(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1807 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1808 | EmitUint8(0xF7); |
| 1809 | EmitOperand(4, address); |
| 1810 | } |
| 1811 | |
| 1812 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1813 | void X86Assembler::sbbl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1814 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1815 | EmitUint8(0x1B); |
| 1816 | EmitOperand(dst, Operand(src)); |
| 1817 | } |
| 1818 | |
| 1819 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1820 | void X86Assembler::sbbl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1821 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1822 | EmitComplex(3, Operand(reg), imm); |
| 1823 | } |
| 1824 | |
| 1825 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1826 | void X86Assembler::sbbl(Register dst, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1827 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1828 | EmitUint8(0x1B); |
| 1829 | EmitOperand(dst, address); |
| 1830 | } |
| 1831 | |
| 1832 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1833 | void X86Assembler::sbbl(const Address& address, Register src) { |
| 1834 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1835 | EmitUint8(0x19); |
| 1836 | EmitOperand(src, address); |
| 1837 | } |
| 1838 | |
| 1839 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1840 | void X86Assembler::incl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1841 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1842 | EmitUint8(0x40 + reg); |
| 1843 | } |
| 1844 | |
| 1845 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1846 | void X86Assembler::incl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1847 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1848 | EmitUint8(0xFF); |
| 1849 | EmitOperand(0, address); |
| 1850 | } |
| 1851 | |
| 1852 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1853 | void X86Assembler::decl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1854 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1855 | EmitUint8(0x48 + reg); |
| 1856 | } |
| 1857 | |
| 1858 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1859 | void X86Assembler::decl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1860 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1861 | EmitUint8(0xFF); |
| 1862 | EmitOperand(1, address); |
| 1863 | } |
| 1864 | |
| 1865 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1866 | void X86Assembler::shll(Register reg, const Immediate& imm) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1867 | EmitGenericShift(4, Operand(reg), imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1868 | } |
| 1869 | |
| 1870 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1871 | void X86Assembler::shll(Register operand, Register shifter) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1872 | EmitGenericShift(4, Operand(operand), shifter); |
| 1873 | } |
| 1874 | |
| 1875 | |
| 1876 | void X86Assembler::shll(const Address& address, const Immediate& imm) { |
| 1877 | EmitGenericShift(4, address, imm); |
| 1878 | } |
| 1879 | |
| 1880 | |
| 1881 | void X86Assembler::shll(const Address& address, Register shifter) { |
| 1882 | EmitGenericShift(4, address, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1883 | } |
| 1884 | |
| 1885 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1886 | void X86Assembler::shrl(Register reg, const Immediate& imm) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1887 | EmitGenericShift(5, Operand(reg), imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1888 | } |
| 1889 | |
| 1890 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1891 | void X86Assembler::shrl(Register operand, Register shifter) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1892 | EmitGenericShift(5, Operand(operand), shifter); |
| 1893 | } |
| 1894 | |
| 1895 | |
| 1896 | void X86Assembler::shrl(const Address& address, const Immediate& imm) { |
| 1897 | EmitGenericShift(5, address, imm); |
| 1898 | } |
| 1899 | |
| 1900 | |
| 1901 | void X86Assembler::shrl(const Address& address, Register shifter) { |
| 1902 | EmitGenericShift(5, address, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1903 | } |
| 1904 | |
| 1905 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1906 | void X86Assembler::sarl(Register reg, const Immediate& imm) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1907 | EmitGenericShift(7, Operand(reg), imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1908 | } |
| 1909 | |
| 1910 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1911 | void X86Assembler::sarl(Register operand, Register shifter) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1912 | EmitGenericShift(7, Operand(operand), shifter); |
| 1913 | } |
| 1914 | |
| 1915 | |
| 1916 | void X86Assembler::sarl(const Address& address, const Immediate& imm) { |
| 1917 | EmitGenericShift(7, address, imm); |
| 1918 | } |
| 1919 | |
| 1920 | |
| 1921 | void X86Assembler::sarl(const Address& address, Register shifter) { |
| 1922 | EmitGenericShift(7, address, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1923 | } |
| 1924 | |
| 1925 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1926 | void X86Assembler::shld(Register dst, Register src, Register shifter) { |
| 1927 | DCHECK_EQ(ECX, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1928 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1929 | EmitUint8(0x0F); |
| 1930 | EmitUint8(0xA5); |
| 1931 | EmitRegisterOperand(src, dst); |
| 1932 | } |
| 1933 | |
| 1934 | |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1935 | void X86Assembler::shld(Register dst, Register src, const Immediate& imm) { |
| 1936 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1937 | EmitUint8(0x0F); |
| 1938 | EmitUint8(0xA4); |
| 1939 | EmitRegisterOperand(src, dst); |
| 1940 | EmitUint8(imm.value() & 0xFF); |
| 1941 | } |
| 1942 | |
| 1943 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1944 | void X86Assembler::shrd(Register dst, Register src, Register shifter) { |
| 1945 | DCHECK_EQ(ECX, shifter); |
| 1946 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1947 | EmitUint8(0x0F); |
| 1948 | EmitUint8(0xAD); |
| 1949 | EmitRegisterOperand(src, dst); |
| 1950 | } |
| 1951 | |
| 1952 | |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1953 | void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) { |
| 1954 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1955 | EmitUint8(0x0F); |
| 1956 | EmitUint8(0xAC); |
| 1957 | EmitRegisterOperand(src, dst); |
| 1958 | EmitUint8(imm.value() & 0xFF); |
| 1959 | } |
| 1960 | |
| 1961 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 1962 | void X86Assembler::roll(Register reg, const Immediate& imm) { |
| 1963 | EmitGenericShift(0, Operand(reg), imm); |
| 1964 | } |
| 1965 | |
| 1966 | |
| 1967 | void X86Assembler::roll(Register operand, Register shifter) { |
| 1968 | EmitGenericShift(0, Operand(operand), shifter); |
| 1969 | } |
| 1970 | |
| 1971 | |
| 1972 | void X86Assembler::rorl(Register reg, const Immediate& imm) { |
| 1973 | EmitGenericShift(1, Operand(reg), imm); |
| 1974 | } |
| 1975 | |
| 1976 | |
| 1977 | void X86Assembler::rorl(Register operand, Register shifter) { |
| 1978 | EmitGenericShift(1, Operand(operand), shifter); |
| 1979 | } |
| 1980 | |
| 1981 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1982 | void X86Assembler::negl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1983 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1984 | EmitUint8(0xF7); |
| 1985 | EmitOperand(3, Operand(reg)); |
| 1986 | } |
| 1987 | |
| 1988 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1989 | void X86Assembler::notl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1990 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1991 | EmitUint8(0xF7); |
| 1992 | EmitUint8(0xD0 | reg); |
| 1993 | } |
| 1994 | |
| 1995 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1996 | void X86Assembler::enter(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1997 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1998 | EmitUint8(0xC8); |
| 1999 | CHECK(imm.is_uint16()); |
| 2000 | EmitUint8(imm.value() & 0xFF); |
| 2001 | EmitUint8((imm.value() >> 8) & 0xFF); |
| 2002 | EmitUint8(0x00); |
| 2003 | } |
| 2004 | |
| 2005 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2006 | void X86Assembler::leave() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2007 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2008 | EmitUint8(0xC9); |
| 2009 | } |
| 2010 | |
| 2011 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2012 | void X86Assembler::ret() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2013 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2014 | EmitUint8(0xC3); |
| 2015 | } |
| 2016 | |
| 2017 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2018 | void X86Assembler::ret(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2019 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2020 | EmitUint8(0xC2); |
| 2021 | CHECK(imm.is_uint16()); |
| 2022 | EmitUint8(imm.value() & 0xFF); |
| 2023 | EmitUint8((imm.value() >> 8) & 0xFF); |
| 2024 | } |
| 2025 | |
| 2026 | |
| 2027 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2028 | void X86Assembler::nop() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2029 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2030 | EmitUint8(0x90); |
| 2031 | } |
| 2032 | |
| 2033 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2034 | void X86Assembler::int3() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2035 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2036 | EmitUint8(0xCC); |
| 2037 | } |
| 2038 | |
| 2039 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2040 | void X86Assembler::hlt() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2041 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2042 | EmitUint8(0xF4); |
| 2043 | } |
| 2044 | |
| 2045 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2046 | void X86Assembler::j(Condition condition, Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2047 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2048 | if (label->IsBound()) { |
| 2049 | static const int kShortSize = 2; |
| 2050 | static const int kLongSize = 6; |
| 2051 | int offset = label->Position() - buffer_.Size(); |
| 2052 | CHECK_LE(offset, 0); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 2053 | if (IsInt<8>(offset - kShortSize)) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2054 | EmitUint8(0x70 + condition); |
| 2055 | EmitUint8((offset - kShortSize) & 0xFF); |
| 2056 | } else { |
| 2057 | EmitUint8(0x0F); |
| 2058 | EmitUint8(0x80 + condition); |
| 2059 | EmitInt32(offset - kLongSize); |
| 2060 | } |
| 2061 | } else { |
| 2062 | EmitUint8(0x0F); |
| 2063 | EmitUint8(0x80 + condition); |
| 2064 | EmitLabelLink(label); |
| 2065 | } |
| 2066 | } |
| 2067 | |
| 2068 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 2069 | void X86Assembler::j(Condition condition, NearLabel* label) { |
| 2070 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2071 | if (label->IsBound()) { |
| 2072 | static const int kShortSize = 2; |
| 2073 | int offset = label->Position() - buffer_.Size(); |
| 2074 | CHECK_LE(offset, 0); |
| 2075 | CHECK(IsInt<8>(offset - kShortSize)); |
| 2076 | EmitUint8(0x70 + condition); |
| 2077 | EmitUint8((offset - kShortSize) & 0xFF); |
| 2078 | } else { |
| 2079 | EmitUint8(0x70 + condition); |
| 2080 | EmitLabelLink(label); |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | |
| 2085 | void X86Assembler::jecxz(NearLabel* label) { |
| 2086 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2087 | if (label->IsBound()) { |
| 2088 | static const int kShortSize = 2; |
| 2089 | int offset = label->Position() - buffer_.Size(); |
| 2090 | CHECK_LE(offset, 0); |
| 2091 | CHECK(IsInt<8>(offset - kShortSize)); |
| 2092 | EmitUint8(0xE3); |
| 2093 | EmitUint8((offset - kShortSize) & 0xFF); |
| 2094 | } else { |
| 2095 | EmitUint8(0xE3); |
| 2096 | EmitLabelLink(label); |
| 2097 | } |
| 2098 | } |
| 2099 | |
| 2100 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2101 | void X86Assembler::jmp(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2102 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2103 | EmitUint8(0xFF); |
| 2104 | EmitRegisterOperand(4, reg); |
| 2105 | } |
| 2106 | |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 2107 | void X86Assembler::jmp(const Address& address) { |
| 2108 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2109 | EmitUint8(0xFF); |
| 2110 | EmitOperand(4, address); |
| 2111 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2112 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2113 | void X86Assembler::jmp(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2114 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2115 | if (label->IsBound()) { |
| 2116 | static const int kShortSize = 2; |
| 2117 | static const int kLongSize = 5; |
| 2118 | int offset = label->Position() - buffer_.Size(); |
| 2119 | CHECK_LE(offset, 0); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 2120 | if (IsInt<8>(offset - kShortSize)) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2121 | EmitUint8(0xEB); |
| 2122 | EmitUint8((offset - kShortSize) & 0xFF); |
| 2123 | } else { |
| 2124 | EmitUint8(0xE9); |
| 2125 | EmitInt32(offset - kLongSize); |
| 2126 | } |
| 2127 | } else { |
| 2128 | EmitUint8(0xE9); |
| 2129 | EmitLabelLink(label); |
| 2130 | } |
| 2131 | } |
| 2132 | |
| 2133 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 2134 | void X86Assembler::jmp(NearLabel* label) { |
| 2135 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2136 | if (label->IsBound()) { |
| 2137 | static const int kShortSize = 2; |
| 2138 | int offset = label->Position() - buffer_.Size(); |
| 2139 | CHECK_LE(offset, 0); |
| 2140 | CHECK(IsInt<8>(offset - kShortSize)); |
| 2141 | EmitUint8(0xEB); |
| 2142 | EmitUint8((offset - kShortSize) & 0xFF); |
| 2143 | } else { |
| 2144 | EmitUint8(0xEB); |
| 2145 | EmitLabelLink(label); |
| 2146 | } |
| 2147 | } |
| 2148 | |
| 2149 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 2150 | void X86Assembler::repne_scasb() { |
| 2151 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2152 | EmitUint8(0xF2); |
| 2153 | EmitUint8(0xAE); |
| 2154 | } |
| 2155 | |
| 2156 | |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 2157 | void X86Assembler::repne_scasw() { |
| 2158 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2159 | EmitUint8(0x66); |
| 2160 | EmitUint8(0xF2); |
| 2161 | EmitUint8(0xAF); |
| 2162 | } |
| 2163 | |
| 2164 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 2165 | void X86Assembler::repe_cmpsb() { |
| 2166 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2167 | EmitUint8(0xF2); |
| 2168 | EmitUint8(0xA6); |
| 2169 | } |
| 2170 | |
| 2171 | |
agicsaki | 71311f8 | 2015-07-27 11:34:13 -0700 | [diff] [blame] | 2172 | void X86Assembler::repe_cmpsw() { |
| 2173 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2174 | EmitUint8(0x66); |
| 2175 | EmitUint8(0xF3); |
| 2176 | EmitUint8(0xA7); |
| 2177 | } |
| 2178 | |
| 2179 | |
agicsaki | 970abfb | 2015-07-31 10:31:14 -0700 | [diff] [blame] | 2180 | void X86Assembler::repe_cmpsl() { |
| 2181 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2182 | EmitUint8(0xF3); |
| 2183 | EmitUint8(0xA7); |
| 2184 | } |
| 2185 | |
| 2186 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 2187 | void X86Assembler::rep_movsb() { |
| 2188 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2189 | EmitUint8(0xF3); |
| 2190 | EmitUint8(0xA4); |
| 2191 | } |
| 2192 | |
| 2193 | |
Mark Mendell | b9c4bbe | 2015-07-01 14:26:52 -0400 | [diff] [blame] | 2194 | void X86Assembler::rep_movsw() { |
| 2195 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2196 | EmitUint8(0x66); |
| 2197 | EmitUint8(0xF3); |
| 2198 | EmitUint8(0xA5); |
| 2199 | } |
| 2200 | |
| 2201 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2202 | X86Assembler* X86Assembler::lock() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2203 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2204 | EmitUint8(0xF0); |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 2205 | return this; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2206 | } |
| 2207 | |
| 2208 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2209 | void X86Assembler::cmpxchgl(const Address& address, Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2210 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2211 | EmitUint8(0x0F); |
| 2212 | EmitUint8(0xB1); |
| 2213 | EmitOperand(reg, address); |
| 2214 | } |
| 2215 | |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 2216 | |
| 2217 | void X86Assembler::cmpxchg8b(const Address& address) { |
| 2218 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2219 | EmitUint8(0x0F); |
| 2220 | EmitUint8(0xC7); |
| 2221 | EmitOperand(1, address); |
| 2222 | } |
| 2223 | |
| 2224 | |
Elliott Hughes | 79ab9e3 | 2012-03-12 15:41:35 -0700 | [diff] [blame] | 2225 | void X86Assembler::mfence() { |
| 2226 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2227 | EmitUint8(0x0F); |
| 2228 | EmitUint8(0xAE); |
| 2229 | EmitUint8(0xF0); |
| 2230 | } |
| 2231 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2232 | X86Assembler* X86Assembler::fs() { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 2233 | // TODO: fs is a prefix and not an instruction |
| 2234 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2235 | EmitUint8(0x64); |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 2236 | return this; |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 2237 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2238 | |
Ian Rogers | befbd57 | 2014-03-06 01:13:39 -0800 | [diff] [blame] | 2239 | X86Assembler* X86Assembler::gs() { |
| 2240 | // TODO: fs is a prefix and not an instruction |
| 2241 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2242 | EmitUint8(0x65); |
| 2243 | return this; |
| 2244 | } |
| 2245 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2246 | void X86Assembler::AddImmediate(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2247 | int value = imm.value(); |
| 2248 | if (value > 0) { |
| 2249 | if (value == 1) { |
| 2250 | incl(reg); |
| 2251 | } else if (value != 0) { |
| 2252 | addl(reg, imm); |
| 2253 | } |
| 2254 | } else if (value < 0) { |
| 2255 | value = -value; |
| 2256 | if (value == 1) { |
| 2257 | decl(reg); |
| 2258 | } else if (value != 0) { |
| 2259 | subl(reg, Immediate(value)); |
| 2260 | } |
| 2261 | } |
| 2262 | } |
| 2263 | |
| 2264 | |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 2265 | void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) { |
| 2266 | // TODO: Need to have a code constants table. |
| 2267 | pushl(Immediate(High32Bits(value))); |
| 2268 | pushl(Immediate(Low32Bits(value))); |
| 2269 | movsd(dst, Address(ESP, 0)); |
| 2270 | addl(ESP, Immediate(2 * sizeof(int32_t))); |
| 2271 | } |
| 2272 | |
| 2273 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2274 | void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2275 | // TODO: Need to have a code constants table. |
| 2276 | int64_t constant = bit_cast<int64_t, double>(value); |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 2277 | LoadLongConstant(dst, constant); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2278 | } |
| 2279 | |
| 2280 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2281 | void X86Assembler::Align(int alignment, int offset) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2282 | CHECK(IsPowerOfTwo(alignment)); |
| 2283 | // Emit nop instruction until the real position is aligned. |
| 2284 | while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) { |
| 2285 | nop(); |
| 2286 | } |
| 2287 | } |
| 2288 | |
| 2289 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2290 | void X86Assembler::Bind(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2291 | int bound = buffer_.Size(); |
| 2292 | CHECK(!label->IsBound()); // Labels can only be bound once. |
| 2293 | while (label->IsLinked()) { |
| 2294 | int position = label->LinkPosition(); |
| 2295 | int next = buffer_.Load<int32_t>(position); |
| 2296 | buffer_.Store<int32_t>(position, bound - (position + 4)); |
| 2297 | label->position_ = next; |
| 2298 | } |
| 2299 | label->BindTo(bound); |
| 2300 | } |
| 2301 | |
| 2302 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 2303 | void X86Assembler::Bind(NearLabel* label) { |
| 2304 | int bound = buffer_.Size(); |
| 2305 | CHECK(!label->IsBound()); // Labels can only be bound once. |
| 2306 | while (label->IsLinked()) { |
| 2307 | int position = label->LinkPosition(); |
| 2308 | uint8_t delta = buffer_.Load<uint8_t>(position); |
| 2309 | int offset = bound - (position + 1); |
| 2310 | CHECK(IsInt<8>(offset)); |
| 2311 | buffer_.Store<int8_t>(position, offset); |
| 2312 | label->position_ = delta != 0u ? label->position_ - delta : 0; |
| 2313 | } |
| 2314 | label->BindTo(bound); |
| 2315 | } |
| 2316 | |
| 2317 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2318 | void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) { |
| 2319 | CHECK_GE(reg_or_opcode, 0); |
| 2320 | CHECK_LT(reg_or_opcode, 8); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2321 | const int length = operand.length_; |
| 2322 | CHECK_GT(length, 0); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2323 | // Emit the ModRM byte updated with the given reg value. |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2324 | CHECK_EQ(operand.encoding_[0] & 0x38, 0); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2325 | EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3)); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2326 | // Emit the rest of the encoded operand. |
| 2327 | for (int i = 1; i < length; i++) { |
| 2328 | EmitUint8(operand.encoding_[i]); |
| 2329 | } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2330 | AssemblerFixup* fixup = operand.GetFixup(); |
| 2331 | if (fixup != nullptr) { |
| 2332 | EmitFixup(fixup); |
| 2333 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2334 | } |
| 2335 | |
| 2336 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2337 | void X86Assembler::EmitImmediate(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2338 | EmitInt32(imm.value()); |
| 2339 | } |
| 2340 | |
| 2341 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2342 | void X86Assembler::EmitComplex(int reg_or_opcode, |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2343 | const Operand& operand, |
| 2344 | const Immediate& immediate) { |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2345 | CHECK_GE(reg_or_opcode, 0); |
| 2346 | CHECK_LT(reg_or_opcode, 8); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2347 | if (immediate.is_int8()) { |
| 2348 | // Use sign-extended 8-bit immediate. |
| 2349 | EmitUint8(0x83); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2350 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2351 | EmitUint8(immediate.value() & 0xFF); |
| 2352 | } else if (operand.IsRegister(EAX)) { |
| 2353 | // Use short form if the destination is eax. |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2354 | EmitUint8(0x05 + (reg_or_opcode << 3)); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2355 | EmitImmediate(immediate); |
| 2356 | } else { |
| 2357 | EmitUint8(0x81); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2358 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2359 | EmitImmediate(immediate); |
| 2360 | } |
| 2361 | } |
| 2362 | |
| 2363 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2364 | void X86Assembler::EmitLabel(Label* label, int instruction_size) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2365 | if (label->IsBound()) { |
| 2366 | int offset = label->Position() - buffer_.Size(); |
| 2367 | CHECK_LE(offset, 0); |
| 2368 | EmitInt32(offset - instruction_size); |
| 2369 | } else { |
| 2370 | EmitLabelLink(label); |
| 2371 | } |
| 2372 | } |
| 2373 | |
| 2374 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2375 | void X86Assembler::EmitLabelLink(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2376 | CHECK(!label->IsBound()); |
| 2377 | int position = buffer_.Size(); |
| 2378 | EmitInt32(label->position_); |
| 2379 | label->LinkTo(position); |
| 2380 | } |
| 2381 | |
| 2382 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 2383 | void X86Assembler::EmitLabelLink(NearLabel* label) { |
| 2384 | CHECK(!label->IsBound()); |
| 2385 | int position = buffer_.Size(); |
| 2386 | if (label->IsLinked()) { |
| 2387 | // Save the delta in the byte that we have to play with. |
| 2388 | uint32_t delta = position - label->LinkPosition(); |
| 2389 | CHECK(IsUint<8>(delta)); |
| 2390 | EmitUint8(delta & 0xFF); |
| 2391 | } else { |
| 2392 | EmitUint8(0); |
| 2393 | } |
| 2394 | label->LinkTo(position); |
| 2395 | } |
| 2396 | |
| 2397 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2398 | void X86Assembler::EmitGenericShift(int reg_or_opcode, |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2399 | const Operand& operand, |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2400 | const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2401 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2402 | CHECK(imm.is_int8()); |
| 2403 | if (imm.value() == 1) { |
| 2404 | EmitUint8(0xD1); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2405 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2406 | } else { |
| 2407 | EmitUint8(0xC1); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2408 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2409 | EmitUint8(imm.value() & 0xFF); |
| 2410 | } |
| 2411 | } |
| 2412 | |
| 2413 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2414 | void X86Assembler::EmitGenericShift(int reg_or_opcode, |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2415 | const Operand& operand, |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2416 | Register shifter) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2417 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2418 | CHECK_EQ(shifter, ECX); |
| 2419 | EmitUint8(0xD3); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2420 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2421 | } |
| 2422 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2423 | void X86Assembler::AddConstantArea() { |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 2424 | ArrayRef<const int32_t> area = constant_area_.GetBuffer(); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2425 | // Generate the data for the literal area. |
| 2426 | for (size_t i = 0, e = area.size(); i < e; i++) { |
| 2427 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2428 | EmitInt32(area[i]); |
| 2429 | } |
| 2430 | } |
| 2431 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2432 | size_t ConstantArea::AppendInt32(int32_t v) { |
| 2433 | size_t result = buffer_.size() * elem_size_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2434 | buffer_.push_back(v); |
| 2435 | return result; |
| 2436 | } |
| 2437 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2438 | size_t ConstantArea::AddInt32(int32_t v) { |
| 2439 | for (size_t i = 0, e = buffer_.size(); i < e; i++) { |
| 2440 | if (v == buffer_[i]) { |
| 2441 | return i * elem_size_; |
| 2442 | } |
| 2443 | } |
| 2444 | |
| 2445 | // Didn't match anything. |
| 2446 | return AppendInt32(v); |
| 2447 | } |
| 2448 | |
| 2449 | size_t ConstantArea::AddInt64(int64_t v) { |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2450 | int32_t v_low = Low32Bits(v); |
| 2451 | int32_t v_high = High32Bits(v); |
| 2452 | if (buffer_.size() > 1) { |
| 2453 | // Ensure we don't pass the end of the buffer. |
| 2454 | for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) { |
| 2455 | if (v_low == buffer_[i] && v_high == buffer_[i + 1]) { |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2456 | return i * elem_size_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2457 | } |
| 2458 | } |
| 2459 | } |
| 2460 | |
| 2461 | // Didn't match anything. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2462 | size_t result = buffer_.size() * elem_size_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2463 | buffer_.push_back(v_low); |
| 2464 | buffer_.push_back(v_high); |
| 2465 | return result; |
| 2466 | } |
| 2467 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2468 | size_t ConstantArea::AddDouble(double v) { |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2469 | // Treat the value as a 64-bit integer value. |
| 2470 | return AddInt64(bit_cast<int64_t, double>(v)); |
| 2471 | } |
| 2472 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2473 | size_t ConstantArea::AddFloat(float v) { |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2474 | // Treat the value as a 32-bit integer value. |
| 2475 | return AddInt32(bit_cast<int32_t, float>(v)); |
| 2476 | } |
| 2477 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2478 | } // namespace x86 |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 2479 | } // namespace art |