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Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Aart Bikc7782262017-01-13 16:20:08 -0800353void X86Assembler::movaps(XmmRegister dst, const Address& src) {
354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0x0F);
356 EmitUint8(0x28);
357 EmitOperand(dst, src);
358}
359
360
361void X86Assembler::movups(XmmRegister dst, const Address& src) {
362 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363 EmitUint8(0x0F);
364 EmitUint8(0x10);
365 EmitOperand(dst, src);
366}
367
368
369void X86Assembler::movaps(const Address& dst, XmmRegister src) {
370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
371 EmitUint8(0x0F);
372 EmitUint8(0x29);
373 EmitOperand(src, dst);
374}
375
376
377void X86Assembler::movups(const Address& dst, XmmRegister src) {
378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
379 EmitUint8(0x0F);
380 EmitUint8(0x11);
381 EmitOperand(src, dst);
382}
383
384
Ian Rogers2c8f6532011-09-02 17:16:34 -0700385void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
387 EmitUint8(0xF3);
388 EmitUint8(0x0F);
389 EmitUint8(0x10);
390 EmitOperand(dst, src);
391}
392
393
Ian Rogers2c8f6532011-09-02 17:16:34 -0700394void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
396 EmitUint8(0xF3);
397 EmitUint8(0x0F);
398 EmitUint8(0x11);
399 EmitOperand(src, dst);
400}
401
402
Ian Rogers2c8f6532011-09-02 17:16:34 -0700403void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700404 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
405 EmitUint8(0xF3);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitXmmRegisterOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0x66);
415 EmitUint8(0x0F);
416 EmitUint8(0x6E);
417 EmitOperand(dst, Operand(src));
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0x66);
424 EmitUint8(0x0F);
425 EmitUint8(0x7E);
426 EmitOperand(src, Operand(dst));
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x58);
435 EmitXmmRegisterOperand(dst, src);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0xF3);
442 EmitUint8(0x0F);
443 EmitUint8(0x58);
444 EmitOperand(dst, src);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0xF3);
451 EmitUint8(0x0F);
452 EmitUint8(0x5C);
453 EmitXmmRegisterOperand(dst, src);
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x5C);
462 EmitOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x59);
471 EmitXmmRegisterOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x59);
480 EmitOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5E);
489 EmitXmmRegisterOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x5E);
498 EmitOperand(dst, src);
499}
500
501
Aart Bikc7782262017-01-13 16:20:08 -0800502void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0x0F);
505 EmitUint8(0x58);
506 EmitXmmRegisterOperand(dst, src);
507}
508
509
510void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
512 EmitUint8(0x0F);
513 EmitUint8(0x5C);
514 EmitXmmRegisterOperand(dst, src);
515}
516
517
518void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x0F);
521 EmitUint8(0x59);
522 EmitXmmRegisterOperand(dst, src);
523}
524
525
526void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528 EmitUint8(0x0F);
529 EmitUint8(0x5E);
530 EmitXmmRegisterOperand(dst, src);
531}
532
533
534void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
536 EmitUint8(0x66);
537 EmitUint8(0x0F);
538 EmitUint8(0x28);
539 EmitXmmRegisterOperand(dst, src);
540}
541
542
543void X86Assembler::movapd(XmmRegister dst, const Address& src) {
544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
545 EmitUint8(0x66);
546 EmitUint8(0x0F);
547 EmitUint8(0x28);
548 EmitOperand(dst, src);
549}
550
551
552void X86Assembler::movupd(XmmRegister dst, const Address& src) {
553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
554 EmitUint8(0x66);
555 EmitUint8(0x0F);
556 EmitUint8(0x10);
557 EmitOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(const Address& dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x29);
566 EmitOperand(src, dst);
567}
568
569
570void X86Assembler::movupd(const Address& dst, XmmRegister src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x11);
575 EmitOperand(src, dst);
576}
577
578
Ian Rogers2c8f6532011-09-02 17:16:34 -0700579void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0xD9);
582 EmitOperand(0, src);
583}
584
585
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500586void X86Assembler::fsts(const Address& dst) {
587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588 EmitUint8(0xD9);
589 EmitOperand(2, dst);
590}
591
592
Ian Rogers2c8f6532011-09-02 17:16:34 -0700593void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
595 EmitUint8(0xD9);
596 EmitOperand(3, dst);
597}
598
599
Ian Rogers2c8f6532011-09-02 17:16:34 -0700600void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF2);
603 EmitUint8(0x0F);
604 EmitUint8(0x10);
605 EmitOperand(dst, src);
606}
607
608
Ian Rogers2c8f6532011-09-02 17:16:34 -0700609void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0xF2);
612 EmitUint8(0x0F);
613 EmitUint8(0x11);
614 EmitOperand(src, dst);
615}
616
617
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0xF2);
621 EmitUint8(0x0F);
622 EmitUint8(0x11);
623 EmitXmmRegisterOperand(src, dst);
624}
625
626
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000627void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0x66);
630 EmitUint8(0x0F);
631 EmitUint8(0x16);
632 EmitOperand(dst, src);
633}
634
635
636void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0x66);
639 EmitUint8(0x0F);
640 EmitUint8(0x17);
641 EmitOperand(src, dst);
642}
643
644
Ian Rogers2c8f6532011-09-02 17:16:34 -0700645void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF2);
648 EmitUint8(0x0F);
649 EmitUint8(0x58);
650 EmitXmmRegisterOperand(dst, src);
651}
652
653
Ian Rogers2c8f6532011-09-02 17:16:34 -0700654void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0xF2);
657 EmitUint8(0x0F);
658 EmitUint8(0x58);
659 EmitOperand(dst, src);
660}
661
662
Ian Rogers2c8f6532011-09-02 17:16:34 -0700663void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0xF2);
666 EmitUint8(0x0F);
667 EmitUint8(0x5C);
668 EmitXmmRegisterOperand(dst, src);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF2);
675 EmitUint8(0x0F);
676 EmitUint8(0x5C);
677 EmitOperand(dst, src);
678}
679
680
Ian Rogers2c8f6532011-09-02 17:16:34 -0700681void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF2);
684 EmitUint8(0x0F);
685 EmitUint8(0x59);
686 EmitXmmRegisterOperand(dst, src);
687}
688
689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF2);
693 EmitUint8(0x0F);
694 EmitUint8(0x59);
695 EmitOperand(dst, src);
696}
697
698
Ian Rogers2c8f6532011-09-02 17:16:34 -0700699void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0xF2);
702 EmitUint8(0x0F);
703 EmitUint8(0x5E);
704 EmitXmmRegisterOperand(dst, src);
705}
706
707
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
710 EmitUint8(0xF2);
711 EmitUint8(0x0F);
712 EmitUint8(0x5E);
713 EmitOperand(dst, src);
714}
715
716
Aart Bikc7782262017-01-13 16:20:08 -0800717void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
719 EmitUint8(0x66);
720 EmitUint8(0x0F);
721 EmitUint8(0x58);
722 EmitXmmRegisterOperand(dst, src);
723}
724
725
726void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
728 EmitUint8(0x66);
729 EmitUint8(0x0F);
730 EmitUint8(0x5C);
731 EmitXmmRegisterOperand(dst, src);
732}
733
734
735void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
737 EmitUint8(0x66);
738 EmitUint8(0x0F);
739 EmitUint8(0x59);
740 EmitXmmRegisterOperand(dst, src);
741}
742
743
744void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
746 EmitUint8(0x66);
747 EmitUint8(0x0F);
748 EmitUint8(0x5E);
749 EmitXmmRegisterOperand(dst, src);
750}
751
752
Aart Bik68555e92017-02-13 14:28:45 -0800753void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755 EmitUint8(0x66);
756 EmitUint8(0x0F);
757 EmitUint8(0x6F);
758 EmitXmmRegisterOperand(dst, src);
759}
760
761
762void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
764 EmitUint8(0x66);
765 EmitUint8(0x0F);
766 EmitUint8(0x6F);
767 EmitOperand(dst, src);
768}
769
770
771void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
773 EmitUint8(0xF3);
774 EmitUint8(0x0F);
775 EmitUint8(0x6F);
776 EmitOperand(dst, src);
777}
778
779
780void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
782 EmitUint8(0x66);
783 EmitUint8(0x0F);
784 EmitUint8(0x7F);
785 EmitOperand(src, dst);
786}
787
788
789void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791 EmitUint8(0xF3);
792 EmitUint8(0x0F);
793 EmitUint8(0x7F);
794 EmitOperand(src, dst);
795}
796
797
Aart Bike69d7a92017-02-17 11:48:23 -0800798void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
799 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
800 EmitUint8(0x66);
801 EmitUint8(0x0F);
802 EmitUint8(0xFC);
803 EmitXmmRegisterOperand(dst, src);
804}
805
806
807void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
809 EmitUint8(0x66);
810 EmitUint8(0x0F);
811 EmitUint8(0xF8);
812 EmitXmmRegisterOperand(dst, src);
813}
814
815
816void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
818 EmitUint8(0x66);
819 EmitUint8(0x0F);
820 EmitUint8(0xFD);
821 EmitXmmRegisterOperand(dst, src);
822}
823
824
825void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
826 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827 EmitUint8(0x66);
828 EmitUint8(0x0F);
829 EmitUint8(0xF9);
830 EmitXmmRegisterOperand(dst, src);
831}
832
833
834void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836 EmitUint8(0x66);
837 EmitUint8(0x0F);
838 EmitUint8(0xD5);
839 EmitXmmRegisterOperand(dst, src);
840}
841
842
Aart Bik68555e92017-02-13 14:28:45 -0800843void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
845 EmitUint8(0x66);
846 EmitUint8(0x0F);
847 EmitUint8(0xFE);
848 EmitXmmRegisterOperand(dst, src);
849}
850
851
852void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
854 EmitUint8(0x66);
855 EmitUint8(0x0F);
856 EmitUint8(0xFA);
857 EmitXmmRegisterOperand(dst, src);
858}
859
860
861void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0x38);
866 EmitUint8(0x40);
867 EmitXmmRegisterOperand(dst, src);
868}
869
870
Aart Bike69d7a92017-02-17 11:48:23 -0800871void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
872 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
873 EmitUint8(0x66);
874 EmitUint8(0x0F);
875 EmitUint8(0xD4);
876 EmitXmmRegisterOperand(dst, src);
877}
878
879
880void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
881 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
882 EmitUint8(0x66);
883 EmitUint8(0x0F);
884 EmitUint8(0xFB);
885 EmitXmmRegisterOperand(dst, src);
886}
887
888
Ian Rogers2c8f6532011-09-02 17:16:34 -0700889void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700890 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
891 EmitUint8(0xF3);
892 EmitUint8(0x0F);
893 EmitUint8(0x2A);
894 EmitOperand(dst, Operand(src));
895}
896
897
Ian Rogers2c8f6532011-09-02 17:16:34 -0700898void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0xF2);
901 EmitUint8(0x0F);
902 EmitUint8(0x2A);
903 EmitOperand(dst, Operand(src));
904}
905
906
Ian Rogers2c8f6532011-09-02 17:16:34 -0700907void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
909 EmitUint8(0xF3);
910 EmitUint8(0x0F);
911 EmitUint8(0x2D);
912 EmitXmmRegisterOperand(dst, src);
913}
914
915
Ian Rogers2c8f6532011-09-02 17:16:34 -0700916void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
918 EmitUint8(0xF3);
919 EmitUint8(0x0F);
920 EmitUint8(0x5A);
921 EmitXmmRegisterOperand(dst, src);
922}
923
924
Ian Rogers2c8f6532011-09-02 17:16:34 -0700925void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700926 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
927 EmitUint8(0xF2);
928 EmitUint8(0x0F);
929 EmitUint8(0x2D);
930 EmitXmmRegisterOperand(dst, src);
931}
932
933
Ian Rogers2c8f6532011-09-02 17:16:34 -0700934void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936 EmitUint8(0xF3);
937 EmitUint8(0x0F);
938 EmitUint8(0x2C);
939 EmitXmmRegisterOperand(dst, src);
940}
941
942
Ian Rogers2c8f6532011-09-02 17:16:34 -0700943void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
945 EmitUint8(0xF2);
946 EmitUint8(0x0F);
947 EmitUint8(0x2C);
948 EmitXmmRegisterOperand(dst, src);
949}
950
951
Ian Rogers2c8f6532011-09-02 17:16:34 -0700952void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954 EmitUint8(0xF2);
955 EmitUint8(0x0F);
956 EmitUint8(0x5A);
957 EmitXmmRegisterOperand(dst, src);
958}
959
960
Aart Bik3ae3b592017-02-24 14:09:15 -0800961void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0x0F);
964 EmitUint8(0x5B);
965 EmitXmmRegisterOperand(dst, src);
966}
967
968
Ian Rogers2c8f6532011-09-02 17:16:34 -0700969void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700970 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
971 EmitUint8(0xF3);
972 EmitUint8(0x0F);
973 EmitUint8(0xE6);
974 EmitXmmRegisterOperand(dst, src);
975}
976
977
Ian Rogers2c8f6532011-09-02 17:16:34 -0700978void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700979 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
980 EmitUint8(0x0F);
981 EmitUint8(0x2F);
982 EmitXmmRegisterOperand(a, b);
983}
984
985
Aart Bik18ba1212016-08-01 14:11:20 -0700986void X86Assembler::comiss(XmmRegister a, const Address& b) {
987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
988 EmitUint8(0x0F);
989 EmitUint8(0x2F);
990 EmitOperand(a, b);
991}
992
993
Ian Rogers2c8f6532011-09-02 17:16:34 -0700994void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700995 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
996 EmitUint8(0x66);
997 EmitUint8(0x0F);
998 EmitUint8(0x2F);
999 EmitXmmRegisterOperand(a, b);
1000}
1001
1002
Aart Bik18ba1212016-08-01 14:11:20 -07001003void X86Assembler::comisd(XmmRegister a, const Address& b) {
1004 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1005 EmitUint8(0x66);
1006 EmitUint8(0x0F);
1007 EmitUint8(0x2F);
1008 EmitOperand(a, b);
1009}
1010
1011
Calin Juravleddb7df22014-11-25 20:56:51 +00001012void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1013 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1014 EmitUint8(0x0F);
1015 EmitUint8(0x2E);
1016 EmitXmmRegisterOperand(a, b);
1017}
1018
1019
Mark Mendell9f51f262015-10-30 09:21:37 -04001020void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1022 EmitUint8(0x0F);
1023 EmitUint8(0x2E);
1024 EmitOperand(a, b);
1025}
1026
1027
Calin Juravleddb7df22014-11-25 20:56:51 +00001028void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1029 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1030 EmitUint8(0x66);
1031 EmitUint8(0x0F);
1032 EmitUint8(0x2E);
1033 EmitXmmRegisterOperand(a, b);
1034}
1035
1036
Mark Mendell9f51f262015-10-30 09:21:37 -04001037void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1038 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1039 EmitUint8(0x66);
1040 EmitUint8(0x0F);
1041 EmitUint8(0x2E);
1042 EmitOperand(a, b);
1043}
1044
1045
Mark Mendellfb8d2792015-03-31 22:16:59 -04001046void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1047 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1048 EmitUint8(0x66);
1049 EmitUint8(0x0F);
1050 EmitUint8(0x3A);
1051 EmitUint8(0x0B);
1052 EmitXmmRegisterOperand(dst, src);
1053 EmitUint8(imm.value());
1054}
1055
1056
1057void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1058 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1059 EmitUint8(0x66);
1060 EmitUint8(0x0F);
1061 EmitUint8(0x3A);
1062 EmitUint8(0x0A);
1063 EmitXmmRegisterOperand(dst, src);
1064 EmitUint8(imm.value());
1065}
1066
1067
Ian Rogers2c8f6532011-09-02 17:16:34 -07001068void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1070 EmitUint8(0xF2);
1071 EmitUint8(0x0F);
1072 EmitUint8(0x51);
1073 EmitXmmRegisterOperand(dst, src);
1074}
1075
1076
Ian Rogers2c8f6532011-09-02 17:16:34 -07001077void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001078 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1079 EmitUint8(0xF3);
1080 EmitUint8(0x0F);
1081 EmitUint8(0x51);
1082 EmitXmmRegisterOperand(dst, src);
1083}
1084
1085
Ian Rogers2c8f6532011-09-02 17:16:34 -07001086void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001087 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1088 EmitUint8(0x66);
1089 EmitUint8(0x0F);
1090 EmitUint8(0x57);
1091 EmitOperand(dst, src);
1092}
1093
1094
Ian Rogers2c8f6532011-09-02 17:16:34 -07001095void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1097 EmitUint8(0x66);
1098 EmitUint8(0x0F);
1099 EmitUint8(0x57);
1100 EmitXmmRegisterOperand(dst, src);
1101}
1102
1103
Aart Bik68555e92017-02-13 14:28:45 -08001104void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001105 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1106 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001107 EmitUint8(0x57);
1108 EmitOperand(dst, src);
1109}
1110
1111
1112void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1113 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1114 EmitUint8(0x0F);
1115 EmitUint8(0x57);
1116 EmitXmmRegisterOperand(dst, src);
1117}
1118
1119
1120void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1122 EmitUint8(0x66);
1123 EmitUint8(0x0F);
1124 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001125 EmitXmmRegisterOperand(dst, src);
1126}
1127
1128
1129void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131 EmitUint8(0x66);
1132 EmitUint8(0x0F);
1133 EmitUint8(0x54);
1134 EmitXmmRegisterOperand(dst, src);
1135}
1136
1137
Aart Bik68555e92017-02-13 14:28:45 -08001138void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001139 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1140 EmitUint8(0x66);
1141 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001142 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001143 EmitOperand(dst, src);
1144}
1145
1146
Aart Bik68555e92017-02-13 14:28:45 -08001147void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1149 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001150 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001151 EmitXmmRegisterOperand(dst, src);
1152}
1153
1154
Mark Mendell09ed1a32015-03-25 08:30:06 -04001155void X86Assembler::andps(XmmRegister dst, const Address& src) {
1156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1157 EmitUint8(0x0F);
1158 EmitUint8(0x54);
1159 EmitOperand(dst, src);
1160}
1161
1162
Aart Bik68555e92017-02-13 14:28:45 -08001163void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001164 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1165 EmitUint8(0x66);
1166 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001167 EmitUint8(0xDB);
1168 EmitXmmRegisterOperand(dst, src);
1169}
1170
1171
1172void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1173 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1174 EmitUint8(0x66);
1175 EmitUint8(0x0F);
1176 EmitUint8(0x56);
1177 EmitXmmRegisterOperand(dst, src);
1178}
1179
1180
1181void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1182 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1183 EmitUint8(0x0F);
1184 EmitUint8(0x56);
1185 EmitXmmRegisterOperand(dst, src);
1186}
1187
1188
1189void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1191 EmitUint8(0x66);
1192 EmitUint8(0x0F);
1193 EmitUint8(0xEB);
1194 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001195}
1196
1197
Aart Bik12e06ed2017-01-31 16:11:24 -08001198void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1199 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1200 EmitUint8(0x66);
1201 EmitUint8(0x0F);
1202 EmitUint8(0xC6);
1203 EmitXmmRegisterOperand(dst, src);
1204 EmitUint8(imm.value());
1205}
1206
1207
1208void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1209 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1210 EmitUint8(0x0F);
1211 EmitUint8(0xC6);
1212 EmitXmmRegisterOperand(dst, src);
1213 EmitUint8(imm.value());
1214}
1215
1216
Aart Bik68555e92017-02-13 14:28:45 -08001217void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1218 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1219 EmitUint8(0x66);
1220 EmitUint8(0x0F);
1221 EmitUint8(0x70);
1222 EmitXmmRegisterOperand(dst, src);
1223 EmitUint8(imm.value());
1224}
1225
1226
Aart Bike69d7a92017-02-17 11:48:23 -08001227void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1228 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1229 EmitUint8(0x66);
1230 EmitUint8(0x0F);
1231 EmitUint8(0x60);
1232 EmitXmmRegisterOperand(dst, src);
1233}
1234
1235
1236void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1237 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1238 EmitUint8(0x66);
1239 EmitUint8(0x0F);
1240 EmitUint8(0x61);
1241 EmitXmmRegisterOperand(dst, src);
1242}
1243
1244
1245void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1246 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1247 EmitUint8(0x66);
1248 EmitUint8(0x0F);
1249 EmitUint8(0x62);
1250 EmitXmmRegisterOperand(dst, src);
1251}
1252
1253
1254void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1255 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1256 EmitUint8(0x66);
1257 EmitUint8(0x0F);
1258 EmitUint8(0x6C);
1259 EmitXmmRegisterOperand(dst, src);
1260}
1261
1262
1263void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1264 DCHECK(shift_count.is_uint8());
1265 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1266 EmitUint8(0x66);
1267 EmitUint8(0x0F);
1268 EmitUint8(0x71);
1269 EmitXmmRegisterOperand(6, reg);
1270 EmitUint8(shift_count.value());
1271}
1272
1273
1274void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1275 DCHECK(shift_count.is_uint8());
1276 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1277 EmitUint8(0x66);
1278 EmitUint8(0x0F);
1279 EmitUint8(0x72);
1280 EmitXmmRegisterOperand(6, reg);
1281 EmitUint8(shift_count.value());
1282}
1283
1284
1285void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1286 DCHECK(shift_count.is_uint8());
1287 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1288 EmitUint8(0x66);
1289 EmitUint8(0x0F);
1290 EmitUint8(0x73);
1291 EmitXmmRegisterOperand(6, reg);
1292 EmitUint8(shift_count.value());
1293}
1294
1295
1296void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1297 DCHECK(shift_count.is_uint8());
1298 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1299 EmitUint8(0x66);
1300 EmitUint8(0x0F);
1301 EmitUint8(0x71);
1302 EmitXmmRegisterOperand(4, reg);
1303 EmitUint8(shift_count.value());
1304}
1305
1306
1307void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1308 DCHECK(shift_count.is_uint8());
1309 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1310 EmitUint8(0x66);
1311 EmitUint8(0x0F);
1312 EmitUint8(0x72);
1313 EmitXmmRegisterOperand(4, reg);
1314 EmitUint8(shift_count.value());
1315}
1316
1317
1318void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1319 DCHECK(shift_count.is_uint8());
1320 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1321 EmitUint8(0x66);
1322 EmitUint8(0x0F);
1323 EmitUint8(0x71);
1324 EmitXmmRegisterOperand(2, reg);
1325 EmitUint8(shift_count.value());
1326}
1327
1328
1329void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1330 DCHECK(shift_count.is_uint8());
1331 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1332 EmitUint8(0x66);
1333 EmitUint8(0x0F);
1334 EmitUint8(0x72);
1335 EmitXmmRegisterOperand(2, reg);
1336 EmitUint8(shift_count.value());
1337}
1338
1339
1340void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1341 DCHECK(shift_count.is_uint8());
1342 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1343 EmitUint8(0x66);
1344 EmitUint8(0x0F);
1345 EmitUint8(0x73);
1346 EmitXmmRegisterOperand(2, reg);
1347 EmitUint8(shift_count.value());
1348}
1349
1350
1351void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1352 DCHECK(shift_count.is_uint8());
1353 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1354 EmitUint8(0x66);
1355 EmitUint8(0x0F);
1356 EmitUint8(0x73);
1357 EmitXmmRegisterOperand(3, reg);
1358 EmitUint8(shift_count.value());
1359}
1360
1361
Ian Rogers2c8f6532011-09-02 17:16:34 -07001362void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001363 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1364 EmitUint8(0xDD);
1365 EmitOperand(0, src);
1366}
1367
1368
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001369void X86Assembler::fstl(const Address& dst) {
1370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1371 EmitUint8(0xDD);
1372 EmitOperand(2, dst);
1373}
1374
1375
Ian Rogers2c8f6532011-09-02 17:16:34 -07001376void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001377 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1378 EmitUint8(0xDD);
1379 EmitOperand(3, dst);
1380}
1381
1382
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001383void X86Assembler::fstsw() {
1384 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1385 EmitUint8(0x9B);
1386 EmitUint8(0xDF);
1387 EmitUint8(0xE0);
1388}
1389
1390
Ian Rogers2c8f6532011-09-02 17:16:34 -07001391void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001392 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1393 EmitUint8(0xD9);
1394 EmitOperand(7, dst);
1395}
1396
1397
Ian Rogers2c8f6532011-09-02 17:16:34 -07001398void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001399 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1400 EmitUint8(0xD9);
1401 EmitOperand(5, src);
1402}
1403
1404
Ian Rogers2c8f6532011-09-02 17:16:34 -07001405void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001406 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1407 EmitUint8(0xDF);
1408 EmitOperand(7, dst);
1409}
1410
1411
Ian Rogers2c8f6532011-09-02 17:16:34 -07001412void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1414 EmitUint8(0xDB);
1415 EmitOperand(3, dst);
1416}
1417
1418
Ian Rogers2c8f6532011-09-02 17:16:34 -07001419void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001420 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1421 EmitUint8(0xDF);
1422 EmitOperand(5, src);
1423}
1424
1425
Roland Levillain0a186012015-04-13 17:00:20 +01001426void X86Assembler::filds(const Address& src) {
1427 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1428 EmitUint8(0xDB);
1429 EmitOperand(0, src);
1430}
1431
1432
Ian Rogers2c8f6532011-09-02 17:16:34 -07001433void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001434 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1435 EmitUint8(0xD9);
1436 EmitUint8(0xF7);
1437}
1438
1439
Ian Rogers2c8f6532011-09-02 17:16:34 -07001440void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001441 CHECK_LT(index.value(), 7);
1442 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1443 EmitUint8(0xDD);
1444 EmitUint8(0xC0 + index.value());
1445}
1446
1447
Ian Rogers2c8f6532011-09-02 17:16:34 -07001448void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1450 EmitUint8(0xD9);
1451 EmitUint8(0xFE);
1452}
1453
1454
Ian Rogers2c8f6532011-09-02 17:16:34 -07001455void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001456 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1457 EmitUint8(0xD9);
1458 EmitUint8(0xFF);
1459}
1460
1461
Ian Rogers2c8f6532011-09-02 17:16:34 -07001462void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001463 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1464 EmitUint8(0xD9);
1465 EmitUint8(0xF2);
1466}
1467
1468
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001469void X86Assembler::fucompp() {
1470 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1471 EmitUint8(0xDA);
1472 EmitUint8(0xE9);
1473}
1474
1475
1476void X86Assembler::fprem() {
1477 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1478 EmitUint8(0xD9);
1479 EmitUint8(0xF8);
1480}
1481
1482
Ian Rogers2c8f6532011-09-02 17:16:34 -07001483void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001484 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1485 EmitUint8(0x87);
1486 EmitRegisterOperand(dst, src);
1487}
1488
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001489
Ian Rogers7caad772012-03-30 01:07:54 -07001490void X86Assembler::xchgl(Register reg, const Address& address) {
1491 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1492 EmitUint8(0x87);
1493 EmitOperand(reg, address);
1494}
1495
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001496
Serguei Katkov3b625932016-05-06 10:24:17 +06001497void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1498 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1499 EmitUint8(0x80);
1500 EmitOperand(7, address);
1501 EmitUint8(imm.value() & 0xFF);
1502}
1503
1504
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001505void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1506 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1507 EmitUint8(0x66);
1508 EmitComplex(7, address, imm);
1509}
1510
1511
Ian Rogers2c8f6532011-09-02 17:16:34 -07001512void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001513 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1514 EmitComplex(7, Operand(reg), imm);
1515}
1516
1517
Ian Rogers2c8f6532011-09-02 17:16:34 -07001518void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1520 EmitUint8(0x3B);
1521 EmitOperand(reg0, Operand(reg1));
1522}
1523
1524
Ian Rogers2c8f6532011-09-02 17:16:34 -07001525void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001526 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1527 EmitUint8(0x3B);
1528 EmitOperand(reg, address);
1529}
1530
1531
Ian Rogers2c8f6532011-09-02 17:16:34 -07001532void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001533 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1534 EmitUint8(0x03);
1535 EmitRegisterOperand(dst, src);
1536}
1537
1538
Ian Rogers2c8f6532011-09-02 17:16:34 -07001539void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001540 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1541 EmitUint8(0x03);
1542 EmitOperand(reg, address);
1543}
1544
1545
Ian Rogers2c8f6532011-09-02 17:16:34 -07001546void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001547 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1548 EmitUint8(0x39);
1549 EmitOperand(reg, address);
1550}
1551
1552
Ian Rogers2c8f6532011-09-02 17:16:34 -07001553void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001554 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1555 EmitComplex(7, address, imm);
1556}
1557
1558
Ian Rogers2c8f6532011-09-02 17:16:34 -07001559void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001560 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1561 EmitUint8(0x85);
1562 EmitRegisterOperand(reg1, reg2);
1563}
1564
1565
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001566void X86Assembler::testl(Register reg, const Address& address) {
1567 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1568 EmitUint8(0x85);
1569 EmitOperand(reg, address);
1570}
1571
1572
Ian Rogers2c8f6532011-09-02 17:16:34 -07001573void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001574 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1575 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1576 // we only test the byte register to keep the encoding short.
1577 if (immediate.is_uint8() && reg < 4) {
1578 // Use zero-extended 8-bit immediate.
1579 if (reg == EAX) {
1580 EmitUint8(0xA8);
1581 } else {
1582 EmitUint8(0xF6);
1583 EmitUint8(0xC0 + reg);
1584 }
1585 EmitUint8(immediate.value() & 0xFF);
1586 } else if (reg == EAX) {
1587 // Use short form if the destination is EAX.
1588 EmitUint8(0xA9);
1589 EmitImmediate(immediate);
1590 } else {
1591 EmitUint8(0xF7);
1592 EmitOperand(0, Operand(reg));
1593 EmitImmediate(immediate);
1594 }
1595}
1596
1597
Vladimir Marko953437b2016-08-24 08:30:46 +00001598void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1599 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1600 EmitUint8(0xF6);
1601 EmitOperand(EAX, dst);
1602 CHECK(imm.is_int8());
1603 EmitUint8(imm.value() & 0xFF);
1604}
1605
1606
1607void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1608 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1609 EmitUint8(0xF7);
1610 EmitOperand(0, dst);
1611 EmitImmediate(imm);
1612}
1613
1614
Ian Rogers2c8f6532011-09-02 17:16:34 -07001615void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001616 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1617 EmitUint8(0x23);
1618 EmitOperand(dst, Operand(src));
1619}
1620
1621
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001622void X86Assembler::andl(Register reg, const Address& address) {
1623 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1624 EmitUint8(0x23);
1625 EmitOperand(reg, address);
1626}
1627
1628
Ian Rogers2c8f6532011-09-02 17:16:34 -07001629void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001630 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1631 EmitComplex(4, Operand(dst), imm);
1632}
1633
1634
Ian Rogers2c8f6532011-09-02 17:16:34 -07001635void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001636 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1637 EmitUint8(0x0B);
1638 EmitOperand(dst, Operand(src));
1639}
1640
1641
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001642void X86Assembler::orl(Register reg, const Address& address) {
1643 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1644 EmitUint8(0x0B);
1645 EmitOperand(reg, address);
1646}
1647
1648
Ian Rogers2c8f6532011-09-02 17:16:34 -07001649void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001650 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1651 EmitComplex(1, Operand(dst), imm);
1652}
1653
1654
Ian Rogers2c8f6532011-09-02 17:16:34 -07001655void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001656 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1657 EmitUint8(0x33);
1658 EmitOperand(dst, Operand(src));
1659}
1660
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001661
1662void X86Assembler::xorl(Register reg, const Address& address) {
1663 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1664 EmitUint8(0x33);
1665 EmitOperand(reg, address);
1666}
1667
1668
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01001669void X86Assembler::xorl(Register dst, const Immediate& imm) {
1670 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1671 EmitComplex(6, Operand(dst), imm);
1672}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001673
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001674
Ian Rogers2c8f6532011-09-02 17:16:34 -07001675void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001676 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1677 EmitComplex(0, Operand(reg), imm);
1678}
1679
1680
Ian Rogers2c8f6532011-09-02 17:16:34 -07001681void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1683 EmitUint8(0x01);
1684 EmitOperand(reg, address);
1685}
1686
1687
Ian Rogers2c8f6532011-09-02 17:16:34 -07001688void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001689 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1690 EmitComplex(0, address, imm);
1691}
1692
1693
Ian Rogers2c8f6532011-09-02 17:16:34 -07001694void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001695 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1696 EmitComplex(2, Operand(reg), imm);
1697}
1698
1699
Ian Rogers2c8f6532011-09-02 17:16:34 -07001700void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001701 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1702 EmitUint8(0x13);
1703 EmitOperand(dst, Operand(src));
1704}
1705
1706
Ian Rogers2c8f6532011-09-02 17:16:34 -07001707void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001708 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1709 EmitUint8(0x13);
1710 EmitOperand(dst, address);
1711}
1712
1713
Ian Rogers2c8f6532011-09-02 17:16:34 -07001714void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1716 EmitUint8(0x2B);
1717 EmitOperand(dst, Operand(src));
1718}
1719
1720
Ian Rogers2c8f6532011-09-02 17:16:34 -07001721void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001722 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1723 EmitComplex(5, Operand(reg), imm);
1724}
1725
1726
Ian Rogers2c8f6532011-09-02 17:16:34 -07001727void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001728 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1729 EmitUint8(0x2B);
1730 EmitOperand(reg, address);
1731}
1732
1733
Mark Mendell09ed1a32015-03-25 08:30:06 -04001734void X86Assembler::subl(const Address& address, Register reg) {
1735 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1736 EmitUint8(0x29);
1737 EmitOperand(reg, address);
1738}
1739
1740
Ian Rogers2c8f6532011-09-02 17:16:34 -07001741void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1743 EmitUint8(0x99);
1744}
1745
1746
Ian Rogers2c8f6532011-09-02 17:16:34 -07001747void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001748 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1749 EmitUint8(0xF7);
1750 EmitUint8(0xF8 | reg);
1751}
1752
1753
Ian Rogers2c8f6532011-09-02 17:16:34 -07001754void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001755 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1756 EmitUint8(0x0F);
1757 EmitUint8(0xAF);
1758 EmitOperand(dst, Operand(src));
1759}
1760
1761
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001762void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001764 // See whether imm can be represented as a sign-extended 8bit value.
1765 int32_t v32 = static_cast<int32_t>(imm.value());
1766 if (IsInt<8>(v32)) {
1767 // Sign-extension works.
1768 EmitUint8(0x6B);
1769 EmitOperand(dst, Operand(src));
1770 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
1771 } else {
1772 // Not representable, use full immediate.
1773 EmitUint8(0x69);
1774 EmitOperand(dst, Operand(src));
1775 EmitImmediate(imm);
1776 }
1777}
1778
1779
1780void X86Assembler::imull(Register reg, const Immediate& imm) {
1781 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001782}
1783
1784
Ian Rogers2c8f6532011-09-02 17:16:34 -07001785void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001786 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1787 EmitUint8(0x0F);
1788 EmitUint8(0xAF);
1789 EmitOperand(reg, address);
1790}
1791
1792
Ian Rogers2c8f6532011-09-02 17:16:34 -07001793void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001794 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1795 EmitUint8(0xF7);
1796 EmitOperand(5, Operand(reg));
1797}
1798
1799
Ian Rogers2c8f6532011-09-02 17:16:34 -07001800void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001801 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1802 EmitUint8(0xF7);
1803 EmitOperand(5, address);
1804}
1805
1806
Ian Rogers2c8f6532011-09-02 17:16:34 -07001807void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1809 EmitUint8(0xF7);
1810 EmitOperand(4, Operand(reg));
1811}
1812
1813
Ian Rogers2c8f6532011-09-02 17:16:34 -07001814void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001815 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1816 EmitUint8(0xF7);
1817 EmitOperand(4, address);
1818}
1819
1820
Ian Rogers2c8f6532011-09-02 17:16:34 -07001821void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001822 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1823 EmitUint8(0x1B);
1824 EmitOperand(dst, Operand(src));
1825}
1826
1827
Ian Rogers2c8f6532011-09-02 17:16:34 -07001828void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001829 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1830 EmitComplex(3, Operand(reg), imm);
1831}
1832
1833
Ian Rogers2c8f6532011-09-02 17:16:34 -07001834void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1836 EmitUint8(0x1B);
1837 EmitOperand(dst, address);
1838}
1839
1840
Mark Mendell09ed1a32015-03-25 08:30:06 -04001841void X86Assembler::sbbl(const Address& address, Register src) {
1842 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1843 EmitUint8(0x19);
1844 EmitOperand(src, address);
1845}
1846
1847
Ian Rogers2c8f6532011-09-02 17:16:34 -07001848void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001849 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1850 EmitUint8(0x40 + reg);
1851}
1852
1853
Ian Rogers2c8f6532011-09-02 17:16:34 -07001854void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001855 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1856 EmitUint8(0xFF);
1857 EmitOperand(0, address);
1858}
1859
1860
Ian Rogers2c8f6532011-09-02 17:16:34 -07001861void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1863 EmitUint8(0x48 + reg);
1864}
1865
1866
Ian Rogers2c8f6532011-09-02 17:16:34 -07001867void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001868 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1869 EmitUint8(0xFF);
1870 EmitOperand(1, address);
1871}
1872
1873
Ian Rogers2c8f6532011-09-02 17:16:34 -07001874void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001875 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001876}
1877
1878
Ian Rogers2c8f6532011-09-02 17:16:34 -07001879void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001880 EmitGenericShift(4, Operand(operand), shifter);
1881}
1882
1883
1884void X86Assembler::shll(const Address& address, const Immediate& imm) {
1885 EmitGenericShift(4, address, imm);
1886}
1887
1888
1889void X86Assembler::shll(const Address& address, Register shifter) {
1890 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001891}
1892
1893
Ian Rogers2c8f6532011-09-02 17:16:34 -07001894void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001895 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001896}
1897
1898
Ian Rogers2c8f6532011-09-02 17:16:34 -07001899void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001900 EmitGenericShift(5, Operand(operand), shifter);
1901}
1902
1903
1904void X86Assembler::shrl(const Address& address, const Immediate& imm) {
1905 EmitGenericShift(5, address, imm);
1906}
1907
1908
1909void X86Assembler::shrl(const Address& address, Register shifter) {
1910 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001911}
1912
1913
Ian Rogers2c8f6532011-09-02 17:16:34 -07001914void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001915 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001916}
1917
1918
Ian Rogers2c8f6532011-09-02 17:16:34 -07001919void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001920 EmitGenericShift(7, Operand(operand), shifter);
1921}
1922
1923
1924void X86Assembler::sarl(const Address& address, const Immediate& imm) {
1925 EmitGenericShift(7, address, imm);
1926}
1927
1928
1929void X86Assembler::sarl(const Address& address, Register shifter) {
1930 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001931}
1932
1933
Calin Juravle9aec02f2014-11-18 23:06:35 +00001934void X86Assembler::shld(Register dst, Register src, Register shifter) {
1935 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001936 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1937 EmitUint8(0x0F);
1938 EmitUint8(0xA5);
1939 EmitRegisterOperand(src, dst);
1940}
1941
1942
Mark P Mendell73945692015-04-29 14:56:17 +00001943void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
1944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1945 EmitUint8(0x0F);
1946 EmitUint8(0xA4);
1947 EmitRegisterOperand(src, dst);
1948 EmitUint8(imm.value() & 0xFF);
1949}
1950
1951
Calin Juravle9aec02f2014-11-18 23:06:35 +00001952void X86Assembler::shrd(Register dst, Register src, Register shifter) {
1953 DCHECK_EQ(ECX, shifter);
1954 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1955 EmitUint8(0x0F);
1956 EmitUint8(0xAD);
1957 EmitRegisterOperand(src, dst);
1958}
1959
1960
Mark P Mendell73945692015-04-29 14:56:17 +00001961void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
1962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1963 EmitUint8(0x0F);
1964 EmitUint8(0xAC);
1965 EmitRegisterOperand(src, dst);
1966 EmitUint8(imm.value() & 0xFF);
1967}
1968
1969
Mark Mendellbcee0922015-09-15 21:45:01 -04001970void X86Assembler::roll(Register reg, const Immediate& imm) {
1971 EmitGenericShift(0, Operand(reg), imm);
1972}
1973
1974
1975void X86Assembler::roll(Register operand, Register shifter) {
1976 EmitGenericShift(0, Operand(operand), shifter);
1977}
1978
1979
1980void X86Assembler::rorl(Register reg, const Immediate& imm) {
1981 EmitGenericShift(1, Operand(reg), imm);
1982}
1983
1984
1985void X86Assembler::rorl(Register operand, Register shifter) {
1986 EmitGenericShift(1, Operand(operand), shifter);
1987}
1988
1989
Ian Rogers2c8f6532011-09-02 17:16:34 -07001990void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001991 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1992 EmitUint8(0xF7);
1993 EmitOperand(3, Operand(reg));
1994}
1995
1996
Ian Rogers2c8f6532011-09-02 17:16:34 -07001997void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001998 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1999 EmitUint8(0xF7);
2000 EmitUint8(0xD0 | reg);
2001}
2002
2003
Ian Rogers2c8f6532011-09-02 17:16:34 -07002004void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002005 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2006 EmitUint8(0xC8);
2007 CHECK(imm.is_uint16());
2008 EmitUint8(imm.value() & 0xFF);
2009 EmitUint8((imm.value() >> 8) & 0xFF);
2010 EmitUint8(0x00);
2011}
2012
2013
Ian Rogers2c8f6532011-09-02 17:16:34 -07002014void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002015 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2016 EmitUint8(0xC9);
2017}
2018
2019
Ian Rogers2c8f6532011-09-02 17:16:34 -07002020void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2022 EmitUint8(0xC3);
2023}
2024
2025
Ian Rogers2c8f6532011-09-02 17:16:34 -07002026void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002027 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2028 EmitUint8(0xC2);
2029 CHECK(imm.is_uint16());
2030 EmitUint8(imm.value() & 0xFF);
2031 EmitUint8((imm.value() >> 8) & 0xFF);
2032}
2033
2034
2035
Ian Rogers2c8f6532011-09-02 17:16:34 -07002036void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002037 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2038 EmitUint8(0x90);
2039}
2040
2041
Ian Rogers2c8f6532011-09-02 17:16:34 -07002042void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2044 EmitUint8(0xCC);
2045}
2046
2047
Ian Rogers2c8f6532011-09-02 17:16:34 -07002048void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002049 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2050 EmitUint8(0xF4);
2051}
2052
2053
Ian Rogers2c8f6532011-09-02 17:16:34 -07002054void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002055 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2056 if (label->IsBound()) {
2057 static const int kShortSize = 2;
2058 static const int kLongSize = 6;
2059 int offset = label->Position() - buffer_.Size();
2060 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002061 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002062 EmitUint8(0x70 + condition);
2063 EmitUint8((offset - kShortSize) & 0xFF);
2064 } else {
2065 EmitUint8(0x0F);
2066 EmitUint8(0x80 + condition);
2067 EmitInt32(offset - kLongSize);
2068 }
2069 } else {
2070 EmitUint8(0x0F);
2071 EmitUint8(0x80 + condition);
2072 EmitLabelLink(label);
2073 }
2074}
2075
2076
Mark Mendell73f455e2015-08-21 09:30:05 -04002077void X86Assembler::j(Condition condition, NearLabel* label) {
2078 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2079 if (label->IsBound()) {
2080 static const int kShortSize = 2;
2081 int offset = label->Position() - buffer_.Size();
2082 CHECK_LE(offset, 0);
2083 CHECK(IsInt<8>(offset - kShortSize));
2084 EmitUint8(0x70 + condition);
2085 EmitUint8((offset - kShortSize) & 0xFF);
2086 } else {
2087 EmitUint8(0x70 + condition);
2088 EmitLabelLink(label);
2089 }
2090}
2091
2092
2093void X86Assembler::jecxz(NearLabel* label) {
2094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2095 if (label->IsBound()) {
2096 static const int kShortSize = 2;
2097 int offset = label->Position() - buffer_.Size();
2098 CHECK_LE(offset, 0);
2099 CHECK(IsInt<8>(offset - kShortSize));
2100 EmitUint8(0xE3);
2101 EmitUint8((offset - kShortSize) & 0xFF);
2102 } else {
2103 EmitUint8(0xE3);
2104 EmitLabelLink(label);
2105 }
2106}
2107
2108
Ian Rogers2c8f6532011-09-02 17:16:34 -07002109void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002110 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2111 EmitUint8(0xFF);
2112 EmitRegisterOperand(4, reg);
2113}
2114
Ian Rogers7caad772012-03-30 01:07:54 -07002115void X86Assembler::jmp(const Address& address) {
2116 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2117 EmitUint8(0xFF);
2118 EmitOperand(4, address);
2119}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002120
Ian Rogers2c8f6532011-09-02 17:16:34 -07002121void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002122 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2123 if (label->IsBound()) {
2124 static const int kShortSize = 2;
2125 static const int kLongSize = 5;
2126 int offset = label->Position() - buffer_.Size();
2127 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002128 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002129 EmitUint8(0xEB);
2130 EmitUint8((offset - kShortSize) & 0xFF);
2131 } else {
2132 EmitUint8(0xE9);
2133 EmitInt32(offset - kLongSize);
2134 }
2135 } else {
2136 EmitUint8(0xE9);
2137 EmitLabelLink(label);
2138 }
2139}
2140
2141
Mark Mendell73f455e2015-08-21 09:30:05 -04002142void X86Assembler::jmp(NearLabel* label) {
2143 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2144 if (label->IsBound()) {
2145 static const int kShortSize = 2;
2146 int offset = label->Position() - buffer_.Size();
2147 CHECK_LE(offset, 0);
2148 CHECK(IsInt<8>(offset - kShortSize));
2149 EmitUint8(0xEB);
2150 EmitUint8((offset - kShortSize) & 0xFF);
2151 } else {
2152 EmitUint8(0xEB);
2153 EmitLabelLink(label);
2154 }
2155}
2156
2157
jessicahandojob03d6402016-09-07 12:16:53 -07002158void X86Assembler::repne_scasb() {
2159 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2160 EmitUint8(0xF2);
2161 EmitUint8(0xAE);
2162}
2163
2164
Andreas Gampe21030dd2015-05-07 14:46:15 -07002165void X86Assembler::repne_scasw() {
2166 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2167 EmitUint8(0x66);
2168 EmitUint8(0xF2);
2169 EmitUint8(0xAF);
2170}
2171
2172
jessicahandojob03d6402016-09-07 12:16:53 -07002173void X86Assembler::repe_cmpsb() {
2174 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2175 EmitUint8(0xF2);
2176 EmitUint8(0xA6);
2177}
2178
2179
agicsaki71311f82015-07-27 11:34:13 -07002180void X86Assembler::repe_cmpsw() {
2181 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2182 EmitUint8(0x66);
2183 EmitUint8(0xF3);
2184 EmitUint8(0xA7);
2185}
2186
2187
agicsaki970abfb2015-07-31 10:31:14 -07002188void X86Assembler::repe_cmpsl() {
2189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2190 EmitUint8(0xF3);
2191 EmitUint8(0xA7);
2192}
2193
2194
jessicahandojob03d6402016-09-07 12:16:53 -07002195void X86Assembler::rep_movsb() {
2196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2197 EmitUint8(0xF3);
2198 EmitUint8(0xA4);
2199}
2200
2201
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002202void X86Assembler::rep_movsw() {
2203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2204 EmitUint8(0x66);
2205 EmitUint8(0xF3);
2206 EmitUint8(0xA5);
2207}
2208
2209
Ian Rogers2c8f6532011-09-02 17:16:34 -07002210X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002211 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2212 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002213 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002214}
2215
2216
Ian Rogers2c8f6532011-09-02 17:16:34 -07002217void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002218 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2219 EmitUint8(0x0F);
2220 EmitUint8(0xB1);
2221 EmitOperand(reg, address);
2222}
2223
Mark Mendell58d25fd2015-04-03 14:52:31 -04002224
2225void X86Assembler::cmpxchg8b(const Address& address) {
2226 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2227 EmitUint8(0x0F);
2228 EmitUint8(0xC7);
2229 EmitOperand(1, address);
2230}
2231
2232
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002233void X86Assembler::mfence() {
2234 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2235 EmitUint8(0x0F);
2236 EmitUint8(0xAE);
2237 EmitUint8(0xF0);
2238}
2239
Ian Rogers2c8f6532011-09-02 17:16:34 -07002240X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002241 // TODO: fs is a prefix and not an instruction
2242 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2243 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002244 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002245}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002246
Ian Rogersbefbd572014-03-06 01:13:39 -08002247X86Assembler* X86Assembler::gs() {
2248 // TODO: fs is a prefix and not an instruction
2249 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2250 EmitUint8(0x65);
2251 return this;
2252}
2253
Ian Rogers2c8f6532011-09-02 17:16:34 -07002254void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002255 int value = imm.value();
2256 if (value > 0) {
2257 if (value == 1) {
2258 incl(reg);
2259 } else if (value != 0) {
2260 addl(reg, imm);
2261 }
2262 } else if (value < 0) {
2263 value = -value;
2264 if (value == 1) {
2265 decl(reg);
2266 } else if (value != 0) {
2267 subl(reg, Immediate(value));
2268 }
2269 }
2270}
2271
2272
Roland Levillain647b9ed2014-11-27 12:06:00 +00002273void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2274 // TODO: Need to have a code constants table.
2275 pushl(Immediate(High32Bits(value)));
2276 pushl(Immediate(Low32Bits(value)));
2277 movsd(dst, Address(ESP, 0));
2278 addl(ESP, Immediate(2 * sizeof(int32_t)));
2279}
2280
2281
Ian Rogers2c8f6532011-09-02 17:16:34 -07002282void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002283 // TODO: Need to have a code constants table.
2284 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002285 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002286}
2287
2288
Ian Rogers2c8f6532011-09-02 17:16:34 -07002289void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002290 CHECK(IsPowerOfTwo(alignment));
2291 // Emit nop instruction until the real position is aligned.
2292 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2293 nop();
2294 }
2295}
2296
2297
Ian Rogers2c8f6532011-09-02 17:16:34 -07002298void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002299 int bound = buffer_.Size();
2300 CHECK(!label->IsBound()); // Labels can only be bound once.
2301 while (label->IsLinked()) {
2302 int position = label->LinkPosition();
2303 int next = buffer_.Load<int32_t>(position);
2304 buffer_.Store<int32_t>(position, bound - (position + 4));
2305 label->position_ = next;
2306 }
2307 label->BindTo(bound);
2308}
2309
2310
Mark Mendell73f455e2015-08-21 09:30:05 -04002311void X86Assembler::Bind(NearLabel* label) {
2312 int bound = buffer_.Size();
2313 CHECK(!label->IsBound()); // Labels can only be bound once.
2314 while (label->IsLinked()) {
2315 int position = label->LinkPosition();
2316 uint8_t delta = buffer_.Load<uint8_t>(position);
2317 int offset = bound - (position + 1);
2318 CHECK(IsInt<8>(offset));
2319 buffer_.Store<int8_t>(position, offset);
2320 label->position_ = delta != 0u ? label->position_ - delta : 0;
2321 }
2322 label->BindTo(bound);
2323}
2324
2325
Ian Rogers44fb0d02012-03-23 16:46:24 -07002326void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2327 CHECK_GE(reg_or_opcode, 0);
2328 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002329 const int length = operand.length_;
2330 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002331 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002332 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002333 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002334 // Emit the rest of the encoded operand.
2335 for (int i = 1; i < length; i++) {
2336 EmitUint8(operand.encoding_[i]);
2337 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002338 AssemblerFixup* fixup = operand.GetFixup();
2339 if (fixup != nullptr) {
2340 EmitFixup(fixup);
2341 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002342}
2343
2344
Ian Rogers2c8f6532011-09-02 17:16:34 -07002345void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002346 EmitInt32(imm.value());
2347}
2348
2349
Ian Rogers44fb0d02012-03-23 16:46:24 -07002350void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002351 const Operand& operand,
2352 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002353 CHECK_GE(reg_or_opcode, 0);
2354 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002355 if (immediate.is_int8()) {
2356 // Use sign-extended 8-bit immediate.
2357 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002358 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002359 EmitUint8(immediate.value() & 0xFF);
2360 } else if (operand.IsRegister(EAX)) {
2361 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002362 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002363 EmitImmediate(immediate);
2364 } else {
2365 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002366 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002367 EmitImmediate(immediate);
2368 }
2369}
2370
2371
Ian Rogers2c8f6532011-09-02 17:16:34 -07002372void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002373 if (label->IsBound()) {
2374 int offset = label->Position() - buffer_.Size();
2375 CHECK_LE(offset, 0);
2376 EmitInt32(offset - instruction_size);
2377 } else {
2378 EmitLabelLink(label);
2379 }
2380}
2381
2382
Ian Rogers2c8f6532011-09-02 17:16:34 -07002383void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002384 CHECK(!label->IsBound());
2385 int position = buffer_.Size();
2386 EmitInt32(label->position_);
2387 label->LinkTo(position);
2388}
2389
2390
Mark Mendell73f455e2015-08-21 09:30:05 -04002391void X86Assembler::EmitLabelLink(NearLabel* label) {
2392 CHECK(!label->IsBound());
2393 int position = buffer_.Size();
2394 if (label->IsLinked()) {
2395 // Save the delta in the byte that we have to play with.
2396 uint32_t delta = position - label->LinkPosition();
2397 CHECK(IsUint<8>(delta));
2398 EmitUint8(delta & 0xFF);
2399 } else {
2400 EmitUint8(0);
2401 }
2402 label->LinkTo(position);
2403}
2404
2405
Ian Rogers44fb0d02012-03-23 16:46:24 -07002406void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002407 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002408 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002409 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2410 CHECK(imm.is_int8());
2411 if (imm.value() == 1) {
2412 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002413 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002414 } else {
2415 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002416 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002417 EmitUint8(imm.value() & 0xFF);
2418 }
2419}
2420
2421
Ian Rogers44fb0d02012-03-23 16:46:24 -07002422void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002423 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002424 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002425 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2426 CHECK_EQ(shifter, ECX);
2427 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002428 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002429}
2430
Mark Mendell0616ae02015-04-17 12:49:27 -04002431void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002432 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002433 // Generate the data for the literal area.
2434 for (size_t i = 0, e = area.size(); i < e; i++) {
2435 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2436 EmitInt32(area[i]);
2437 }
2438}
2439
Mark Mendell805b3b52015-09-18 14:10:29 -04002440size_t ConstantArea::AppendInt32(int32_t v) {
2441 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002442 buffer_.push_back(v);
2443 return result;
2444}
2445
Mark Mendell805b3b52015-09-18 14:10:29 -04002446size_t ConstantArea::AddInt32(int32_t v) {
2447 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2448 if (v == buffer_[i]) {
2449 return i * elem_size_;
2450 }
2451 }
2452
2453 // Didn't match anything.
2454 return AppendInt32(v);
2455}
2456
2457size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002458 int32_t v_low = Low32Bits(v);
2459 int32_t v_high = High32Bits(v);
2460 if (buffer_.size() > 1) {
2461 // Ensure we don't pass the end of the buffer.
2462 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2463 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002464 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002465 }
2466 }
2467 }
2468
2469 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002470 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002471 buffer_.push_back(v_low);
2472 buffer_.push_back(v_high);
2473 return result;
2474}
2475
Mark Mendell805b3b52015-09-18 14:10:29 -04002476size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002477 // Treat the value as a 64-bit integer value.
2478 return AddInt64(bit_cast<int64_t, double>(v));
2479}
2480
Mark Mendell805b3b52015-09-18 14:10:29 -04002481size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002482 // Treat the value as a 32-bit integer value.
2483 return AddInt32(bit_cast<int32_t, float>(v));
2484}
2485
Ian Rogers2c8f6532011-09-02 17:16:34 -07002486} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002487} // namespace art