blob: 0a6ceefe69ea6ce07a0376f36e2d70a35b96db75 [file] [log] [blame]
Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Aart Bikc7782262017-01-13 16:20:08 -0800353void X86Assembler::movaps(XmmRegister dst, const Address& src) {
354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0x0F);
356 EmitUint8(0x28);
357 EmitOperand(dst, src);
358}
359
360
361void X86Assembler::movups(XmmRegister dst, const Address& src) {
362 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363 EmitUint8(0x0F);
364 EmitUint8(0x10);
365 EmitOperand(dst, src);
366}
367
368
369void X86Assembler::movaps(const Address& dst, XmmRegister src) {
370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
371 EmitUint8(0x0F);
372 EmitUint8(0x29);
373 EmitOperand(src, dst);
374}
375
376
377void X86Assembler::movups(const Address& dst, XmmRegister src) {
378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
379 EmitUint8(0x0F);
380 EmitUint8(0x11);
381 EmitOperand(src, dst);
382}
383
384
Ian Rogers2c8f6532011-09-02 17:16:34 -0700385void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
387 EmitUint8(0xF3);
388 EmitUint8(0x0F);
389 EmitUint8(0x10);
390 EmitOperand(dst, src);
391}
392
393
Ian Rogers2c8f6532011-09-02 17:16:34 -0700394void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
396 EmitUint8(0xF3);
397 EmitUint8(0x0F);
398 EmitUint8(0x11);
399 EmitOperand(src, dst);
400}
401
402
Ian Rogers2c8f6532011-09-02 17:16:34 -0700403void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700404 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
405 EmitUint8(0xF3);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitXmmRegisterOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0x66);
415 EmitUint8(0x0F);
416 EmitUint8(0x6E);
417 EmitOperand(dst, Operand(src));
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0x66);
424 EmitUint8(0x0F);
425 EmitUint8(0x7E);
426 EmitOperand(src, Operand(dst));
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x58);
435 EmitXmmRegisterOperand(dst, src);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0xF3);
442 EmitUint8(0x0F);
443 EmitUint8(0x58);
444 EmitOperand(dst, src);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0xF3);
451 EmitUint8(0x0F);
452 EmitUint8(0x5C);
453 EmitXmmRegisterOperand(dst, src);
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x5C);
462 EmitOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x59);
471 EmitXmmRegisterOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x59);
480 EmitOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5E);
489 EmitXmmRegisterOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x5E);
498 EmitOperand(dst, src);
499}
500
501
Aart Bikc7782262017-01-13 16:20:08 -0800502void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0x0F);
505 EmitUint8(0x58);
506 EmitXmmRegisterOperand(dst, src);
507}
508
509
510void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
512 EmitUint8(0x0F);
513 EmitUint8(0x5C);
514 EmitXmmRegisterOperand(dst, src);
515}
516
517
518void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x0F);
521 EmitUint8(0x59);
522 EmitXmmRegisterOperand(dst, src);
523}
524
525
526void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528 EmitUint8(0x0F);
529 EmitUint8(0x5E);
530 EmitXmmRegisterOperand(dst, src);
531}
532
533
534void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
536 EmitUint8(0x66);
537 EmitUint8(0x0F);
538 EmitUint8(0x28);
539 EmitXmmRegisterOperand(dst, src);
540}
541
542
543void X86Assembler::movapd(XmmRegister dst, const Address& src) {
544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
545 EmitUint8(0x66);
546 EmitUint8(0x0F);
547 EmitUint8(0x28);
548 EmitOperand(dst, src);
549}
550
551
552void X86Assembler::movupd(XmmRegister dst, const Address& src) {
553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
554 EmitUint8(0x66);
555 EmitUint8(0x0F);
556 EmitUint8(0x10);
557 EmitOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(const Address& dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x29);
566 EmitOperand(src, dst);
567}
568
569
570void X86Assembler::movupd(const Address& dst, XmmRegister src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x11);
575 EmitOperand(src, dst);
576}
577
578
Ian Rogers2c8f6532011-09-02 17:16:34 -0700579void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0xD9);
582 EmitOperand(0, src);
583}
584
585
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500586void X86Assembler::fsts(const Address& dst) {
587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588 EmitUint8(0xD9);
589 EmitOperand(2, dst);
590}
591
592
Ian Rogers2c8f6532011-09-02 17:16:34 -0700593void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
595 EmitUint8(0xD9);
596 EmitOperand(3, dst);
597}
598
599
Ian Rogers2c8f6532011-09-02 17:16:34 -0700600void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF2);
603 EmitUint8(0x0F);
604 EmitUint8(0x10);
605 EmitOperand(dst, src);
606}
607
608
Ian Rogers2c8f6532011-09-02 17:16:34 -0700609void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0xF2);
612 EmitUint8(0x0F);
613 EmitUint8(0x11);
614 EmitOperand(src, dst);
615}
616
617
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0xF2);
621 EmitUint8(0x0F);
622 EmitUint8(0x11);
623 EmitXmmRegisterOperand(src, dst);
624}
625
626
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000627void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0x66);
630 EmitUint8(0x0F);
631 EmitUint8(0x16);
632 EmitOperand(dst, src);
633}
634
635
636void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0x66);
639 EmitUint8(0x0F);
640 EmitUint8(0x17);
641 EmitOperand(src, dst);
642}
643
644
Ian Rogers2c8f6532011-09-02 17:16:34 -0700645void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF2);
648 EmitUint8(0x0F);
649 EmitUint8(0x58);
650 EmitXmmRegisterOperand(dst, src);
651}
652
653
Ian Rogers2c8f6532011-09-02 17:16:34 -0700654void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0xF2);
657 EmitUint8(0x0F);
658 EmitUint8(0x58);
659 EmitOperand(dst, src);
660}
661
662
Ian Rogers2c8f6532011-09-02 17:16:34 -0700663void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0xF2);
666 EmitUint8(0x0F);
667 EmitUint8(0x5C);
668 EmitXmmRegisterOperand(dst, src);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF2);
675 EmitUint8(0x0F);
676 EmitUint8(0x5C);
677 EmitOperand(dst, src);
678}
679
680
Ian Rogers2c8f6532011-09-02 17:16:34 -0700681void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF2);
684 EmitUint8(0x0F);
685 EmitUint8(0x59);
686 EmitXmmRegisterOperand(dst, src);
687}
688
689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF2);
693 EmitUint8(0x0F);
694 EmitUint8(0x59);
695 EmitOperand(dst, src);
696}
697
698
Ian Rogers2c8f6532011-09-02 17:16:34 -0700699void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0xF2);
702 EmitUint8(0x0F);
703 EmitUint8(0x5E);
704 EmitXmmRegisterOperand(dst, src);
705}
706
707
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
710 EmitUint8(0xF2);
711 EmitUint8(0x0F);
712 EmitUint8(0x5E);
713 EmitOperand(dst, src);
714}
715
716
Aart Bikc7782262017-01-13 16:20:08 -0800717void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
719 EmitUint8(0x66);
720 EmitUint8(0x0F);
721 EmitUint8(0x58);
722 EmitXmmRegisterOperand(dst, src);
723}
724
725
726void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
728 EmitUint8(0x66);
729 EmitUint8(0x0F);
730 EmitUint8(0x5C);
731 EmitXmmRegisterOperand(dst, src);
732}
733
734
735void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
737 EmitUint8(0x66);
738 EmitUint8(0x0F);
739 EmitUint8(0x59);
740 EmitXmmRegisterOperand(dst, src);
741}
742
743
744void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
746 EmitUint8(0x66);
747 EmitUint8(0x0F);
748 EmitUint8(0x5E);
749 EmitXmmRegisterOperand(dst, src);
750}
751
752
Aart Bik68555e92017-02-13 14:28:45 -0800753void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755 EmitUint8(0x66);
756 EmitUint8(0x0F);
757 EmitUint8(0x6F);
758 EmitXmmRegisterOperand(dst, src);
759}
760
761
762void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
764 EmitUint8(0x66);
765 EmitUint8(0x0F);
766 EmitUint8(0x6F);
767 EmitOperand(dst, src);
768}
769
770
771void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
773 EmitUint8(0xF3);
774 EmitUint8(0x0F);
775 EmitUint8(0x6F);
776 EmitOperand(dst, src);
777}
778
779
780void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
782 EmitUint8(0x66);
783 EmitUint8(0x0F);
784 EmitUint8(0x7F);
785 EmitOperand(src, dst);
786}
787
788
789void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791 EmitUint8(0xF3);
792 EmitUint8(0x0F);
793 EmitUint8(0x7F);
794 EmitOperand(src, dst);
795}
796
797
Aart Bike69d7a92017-02-17 11:48:23 -0800798void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
799 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
800 EmitUint8(0x66);
801 EmitUint8(0x0F);
802 EmitUint8(0xFC);
803 EmitXmmRegisterOperand(dst, src);
804}
805
806
807void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
809 EmitUint8(0x66);
810 EmitUint8(0x0F);
811 EmitUint8(0xF8);
812 EmitXmmRegisterOperand(dst, src);
813}
814
815
816void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
818 EmitUint8(0x66);
819 EmitUint8(0x0F);
820 EmitUint8(0xFD);
821 EmitXmmRegisterOperand(dst, src);
822}
823
824
825void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
826 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827 EmitUint8(0x66);
828 EmitUint8(0x0F);
829 EmitUint8(0xF9);
830 EmitXmmRegisterOperand(dst, src);
831}
832
833
834void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836 EmitUint8(0x66);
837 EmitUint8(0x0F);
838 EmitUint8(0xD5);
839 EmitXmmRegisterOperand(dst, src);
840}
841
842
Aart Bik68555e92017-02-13 14:28:45 -0800843void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
845 EmitUint8(0x66);
846 EmitUint8(0x0F);
847 EmitUint8(0xFE);
848 EmitXmmRegisterOperand(dst, src);
849}
850
851
852void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
854 EmitUint8(0x66);
855 EmitUint8(0x0F);
856 EmitUint8(0xFA);
857 EmitXmmRegisterOperand(dst, src);
858}
859
860
861void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0x38);
866 EmitUint8(0x40);
867 EmitXmmRegisterOperand(dst, src);
868}
869
870
Aart Bike69d7a92017-02-17 11:48:23 -0800871void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
872 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
873 EmitUint8(0x66);
874 EmitUint8(0x0F);
875 EmitUint8(0xD4);
876 EmitXmmRegisterOperand(dst, src);
877}
878
879
880void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
881 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
882 EmitUint8(0x66);
883 EmitUint8(0x0F);
884 EmitUint8(0xFB);
885 EmitXmmRegisterOperand(dst, src);
886}
887
888
Ian Rogers2c8f6532011-09-02 17:16:34 -0700889void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700890 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
891 EmitUint8(0xF3);
892 EmitUint8(0x0F);
893 EmitUint8(0x2A);
894 EmitOperand(dst, Operand(src));
895}
896
897
Ian Rogers2c8f6532011-09-02 17:16:34 -0700898void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0xF2);
901 EmitUint8(0x0F);
902 EmitUint8(0x2A);
903 EmitOperand(dst, Operand(src));
904}
905
906
Ian Rogers2c8f6532011-09-02 17:16:34 -0700907void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
909 EmitUint8(0xF3);
910 EmitUint8(0x0F);
911 EmitUint8(0x2D);
912 EmitXmmRegisterOperand(dst, src);
913}
914
915
Ian Rogers2c8f6532011-09-02 17:16:34 -0700916void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
918 EmitUint8(0xF3);
919 EmitUint8(0x0F);
920 EmitUint8(0x5A);
921 EmitXmmRegisterOperand(dst, src);
922}
923
924
Ian Rogers2c8f6532011-09-02 17:16:34 -0700925void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700926 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
927 EmitUint8(0xF2);
928 EmitUint8(0x0F);
929 EmitUint8(0x2D);
930 EmitXmmRegisterOperand(dst, src);
931}
932
933
Ian Rogers2c8f6532011-09-02 17:16:34 -0700934void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936 EmitUint8(0xF3);
937 EmitUint8(0x0F);
938 EmitUint8(0x2C);
939 EmitXmmRegisterOperand(dst, src);
940}
941
942
Ian Rogers2c8f6532011-09-02 17:16:34 -0700943void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
945 EmitUint8(0xF2);
946 EmitUint8(0x0F);
947 EmitUint8(0x2C);
948 EmitXmmRegisterOperand(dst, src);
949}
950
951
Ian Rogers2c8f6532011-09-02 17:16:34 -0700952void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954 EmitUint8(0xF2);
955 EmitUint8(0x0F);
956 EmitUint8(0x5A);
957 EmitXmmRegisterOperand(dst, src);
958}
959
960
Aart Bik3ae3b592017-02-24 14:09:15 -0800961void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0x0F);
964 EmitUint8(0x5B);
965 EmitXmmRegisterOperand(dst, src);
966}
967
968
Ian Rogers2c8f6532011-09-02 17:16:34 -0700969void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700970 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
971 EmitUint8(0xF3);
972 EmitUint8(0x0F);
973 EmitUint8(0xE6);
974 EmitXmmRegisterOperand(dst, src);
975}
976
977
Ian Rogers2c8f6532011-09-02 17:16:34 -0700978void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700979 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
980 EmitUint8(0x0F);
981 EmitUint8(0x2F);
982 EmitXmmRegisterOperand(a, b);
983}
984
985
Aart Bik18ba1212016-08-01 14:11:20 -0700986void X86Assembler::comiss(XmmRegister a, const Address& b) {
987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
988 EmitUint8(0x0F);
989 EmitUint8(0x2F);
990 EmitOperand(a, b);
991}
992
993
Ian Rogers2c8f6532011-09-02 17:16:34 -0700994void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700995 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
996 EmitUint8(0x66);
997 EmitUint8(0x0F);
998 EmitUint8(0x2F);
999 EmitXmmRegisterOperand(a, b);
1000}
1001
1002
Aart Bik18ba1212016-08-01 14:11:20 -07001003void X86Assembler::comisd(XmmRegister a, const Address& b) {
1004 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1005 EmitUint8(0x66);
1006 EmitUint8(0x0F);
1007 EmitUint8(0x2F);
1008 EmitOperand(a, b);
1009}
1010
1011
Calin Juravleddb7df22014-11-25 20:56:51 +00001012void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1013 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1014 EmitUint8(0x0F);
1015 EmitUint8(0x2E);
1016 EmitXmmRegisterOperand(a, b);
1017}
1018
1019
Mark Mendell9f51f262015-10-30 09:21:37 -04001020void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1022 EmitUint8(0x0F);
1023 EmitUint8(0x2E);
1024 EmitOperand(a, b);
1025}
1026
1027
Calin Juravleddb7df22014-11-25 20:56:51 +00001028void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1029 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1030 EmitUint8(0x66);
1031 EmitUint8(0x0F);
1032 EmitUint8(0x2E);
1033 EmitXmmRegisterOperand(a, b);
1034}
1035
1036
Mark Mendell9f51f262015-10-30 09:21:37 -04001037void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1038 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1039 EmitUint8(0x66);
1040 EmitUint8(0x0F);
1041 EmitUint8(0x2E);
1042 EmitOperand(a, b);
1043}
1044
1045
Mark Mendellfb8d2792015-03-31 22:16:59 -04001046void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1047 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1048 EmitUint8(0x66);
1049 EmitUint8(0x0F);
1050 EmitUint8(0x3A);
1051 EmitUint8(0x0B);
1052 EmitXmmRegisterOperand(dst, src);
1053 EmitUint8(imm.value());
1054}
1055
1056
1057void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1058 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1059 EmitUint8(0x66);
1060 EmitUint8(0x0F);
1061 EmitUint8(0x3A);
1062 EmitUint8(0x0A);
1063 EmitXmmRegisterOperand(dst, src);
1064 EmitUint8(imm.value());
1065}
1066
1067
Ian Rogers2c8f6532011-09-02 17:16:34 -07001068void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1070 EmitUint8(0xF2);
1071 EmitUint8(0x0F);
1072 EmitUint8(0x51);
1073 EmitXmmRegisterOperand(dst, src);
1074}
1075
1076
Ian Rogers2c8f6532011-09-02 17:16:34 -07001077void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001078 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1079 EmitUint8(0xF3);
1080 EmitUint8(0x0F);
1081 EmitUint8(0x51);
1082 EmitXmmRegisterOperand(dst, src);
1083}
1084
1085
Ian Rogers2c8f6532011-09-02 17:16:34 -07001086void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001087 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1088 EmitUint8(0x66);
1089 EmitUint8(0x0F);
1090 EmitUint8(0x57);
1091 EmitOperand(dst, src);
1092}
1093
1094
Ian Rogers2c8f6532011-09-02 17:16:34 -07001095void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1097 EmitUint8(0x66);
1098 EmitUint8(0x0F);
1099 EmitUint8(0x57);
1100 EmitXmmRegisterOperand(dst, src);
1101}
1102
1103
Aart Bik68555e92017-02-13 14:28:45 -08001104void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001105 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1106 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001107 EmitUint8(0x57);
1108 EmitOperand(dst, src);
1109}
1110
1111
1112void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1113 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1114 EmitUint8(0x0F);
1115 EmitUint8(0x57);
1116 EmitXmmRegisterOperand(dst, src);
1117}
1118
1119
1120void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1122 EmitUint8(0x66);
1123 EmitUint8(0x0F);
1124 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001125 EmitXmmRegisterOperand(dst, src);
1126}
1127
1128
1129void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131 EmitUint8(0x66);
1132 EmitUint8(0x0F);
1133 EmitUint8(0x54);
1134 EmitXmmRegisterOperand(dst, src);
1135}
1136
1137
Aart Bik68555e92017-02-13 14:28:45 -08001138void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001139 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1140 EmitUint8(0x66);
1141 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001142 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001143 EmitOperand(dst, src);
1144}
1145
1146
Aart Bik68555e92017-02-13 14:28:45 -08001147void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1149 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001150 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001151 EmitXmmRegisterOperand(dst, src);
1152}
1153
1154
Mark Mendell09ed1a32015-03-25 08:30:06 -04001155void X86Assembler::andps(XmmRegister dst, const Address& src) {
1156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1157 EmitUint8(0x0F);
1158 EmitUint8(0x54);
1159 EmitOperand(dst, src);
1160}
1161
1162
Aart Bik68555e92017-02-13 14:28:45 -08001163void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001164 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1165 EmitUint8(0x66);
1166 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001167 EmitUint8(0xDB);
1168 EmitXmmRegisterOperand(dst, src);
1169}
1170
1171
Aart Bik21c580b2017-03-13 11:52:07 -07001172void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
1173 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1174 EmitUint8(0x66);
1175 EmitUint8(0x0F);
1176 EmitUint8(0x55);
1177 EmitXmmRegisterOperand(dst, src);
1178}
1179
1180
1181void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
1182 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1183 EmitUint8(0x0F);
1184 EmitUint8(0x55);
1185 EmitXmmRegisterOperand(dst, src);
1186}
1187
1188
1189void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
1190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1191 EmitUint8(0x66);
1192 EmitUint8(0x0F);
1193 EmitUint8(0xDF);
1194 EmitXmmRegisterOperand(dst, src);
1195}
1196
1197
Aart Bik68555e92017-02-13 14:28:45 -08001198void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1199 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1200 EmitUint8(0x66);
1201 EmitUint8(0x0F);
1202 EmitUint8(0x56);
1203 EmitXmmRegisterOperand(dst, src);
1204}
1205
1206
1207void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1208 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1209 EmitUint8(0x0F);
1210 EmitUint8(0x56);
1211 EmitXmmRegisterOperand(dst, src);
1212}
1213
1214
1215void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1216 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1217 EmitUint8(0x66);
1218 EmitUint8(0x0F);
1219 EmitUint8(0xEB);
1220 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001221}
1222
1223
Aart Bik12e06ed2017-01-31 16:11:24 -08001224void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1226 EmitUint8(0x66);
1227 EmitUint8(0x0F);
1228 EmitUint8(0xC6);
1229 EmitXmmRegisterOperand(dst, src);
1230 EmitUint8(imm.value());
1231}
1232
1233
1234void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1235 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1236 EmitUint8(0x0F);
1237 EmitUint8(0xC6);
1238 EmitXmmRegisterOperand(dst, src);
1239 EmitUint8(imm.value());
1240}
1241
1242
Aart Bik68555e92017-02-13 14:28:45 -08001243void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1244 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1245 EmitUint8(0x66);
1246 EmitUint8(0x0F);
1247 EmitUint8(0x70);
1248 EmitXmmRegisterOperand(dst, src);
1249 EmitUint8(imm.value());
1250}
1251
1252
Aart Bike69d7a92017-02-17 11:48:23 -08001253void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1254 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1255 EmitUint8(0x66);
1256 EmitUint8(0x0F);
1257 EmitUint8(0x60);
1258 EmitXmmRegisterOperand(dst, src);
1259}
1260
1261
1262void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1263 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1264 EmitUint8(0x66);
1265 EmitUint8(0x0F);
1266 EmitUint8(0x61);
1267 EmitXmmRegisterOperand(dst, src);
1268}
1269
1270
1271void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1272 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1273 EmitUint8(0x66);
1274 EmitUint8(0x0F);
1275 EmitUint8(0x62);
1276 EmitXmmRegisterOperand(dst, src);
1277}
1278
1279
1280void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1281 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1282 EmitUint8(0x66);
1283 EmitUint8(0x0F);
1284 EmitUint8(0x6C);
1285 EmitXmmRegisterOperand(dst, src);
1286}
1287
1288
1289void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1290 DCHECK(shift_count.is_uint8());
1291 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1292 EmitUint8(0x66);
1293 EmitUint8(0x0F);
1294 EmitUint8(0x71);
1295 EmitXmmRegisterOperand(6, reg);
1296 EmitUint8(shift_count.value());
1297}
1298
1299
1300void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1301 DCHECK(shift_count.is_uint8());
1302 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1303 EmitUint8(0x66);
1304 EmitUint8(0x0F);
1305 EmitUint8(0x72);
1306 EmitXmmRegisterOperand(6, reg);
1307 EmitUint8(shift_count.value());
1308}
1309
1310
1311void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1312 DCHECK(shift_count.is_uint8());
1313 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1314 EmitUint8(0x66);
1315 EmitUint8(0x0F);
1316 EmitUint8(0x73);
1317 EmitXmmRegisterOperand(6, reg);
1318 EmitUint8(shift_count.value());
1319}
1320
1321
1322void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1323 DCHECK(shift_count.is_uint8());
1324 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1325 EmitUint8(0x66);
1326 EmitUint8(0x0F);
1327 EmitUint8(0x71);
1328 EmitXmmRegisterOperand(4, reg);
1329 EmitUint8(shift_count.value());
1330}
1331
1332
1333void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1334 DCHECK(shift_count.is_uint8());
1335 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1336 EmitUint8(0x66);
1337 EmitUint8(0x0F);
1338 EmitUint8(0x72);
1339 EmitXmmRegisterOperand(4, reg);
1340 EmitUint8(shift_count.value());
1341}
1342
1343
1344void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1345 DCHECK(shift_count.is_uint8());
1346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1347 EmitUint8(0x66);
1348 EmitUint8(0x0F);
1349 EmitUint8(0x71);
1350 EmitXmmRegisterOperand(2, reg);
1351 EmitUint8(shift_count.value());
1352}
1353
1354
1355void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1356 DCHECK(shift_count.is_uint8());
1357 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1358 EmitUint8(0x66);
1359 EmitUint8(0x0F);
1360 EmitUint8(0x72);
1361 EmitXmmRegisterOperand(2, reg);
1362 EmitUint8(shift_count.value());
1363}
1364
1365
1366void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1367 DCHECK(shift_count.is_uint8());
1368 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1369 EmitUint8(0x66);
1370 EmitUint8(0x0F);
1371 EmitUint8(0x73);
1372 EmitXmmRegisterOperand(2, reg);
1373 EmitUint8(shift_count.value());
1374}
1375
1376
1377void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1378 DCHECK(shift_count.is_uint8());
1379 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1380 EmitUint8(0x66);
1381 EmitUint8(0x0F);
1382 EmitUint8(0x73);
1383 EmitXmmRegisterOperand(3, reg);
1384 EmitUint8(shift_count.value());
1385}
1386
1387
Ian Rogers2c8f6532011-09-02 17:16:34 -07001388void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001389 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1390 EmitUint8(0xDD);
1391 EmitOperand(0, src);
1392}
1393
1394
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001395void X86Assembler::fstl(const Address& dst) {
1396 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1397 EmitUint8(0xDD);
1398 EmitOperand(2, dst);
1399}
1400
1401
Ian Rogers2c8f6532011-09-02 17:16:34 -07001402void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001403 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1404 EmitUint8(0xDD);
1405 EmitOperand(3, dst);
1406}
1407
1408
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001409void X86Assembler::fstsw() {
1410 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1411 EmitUint8(0x9B);
1412 EmitUint8(0xDF);
1413 EmitUint8(0xE0);
1414}
1415
1416
Ian Rogers2c8f6532011-09-02 17:16:34 -07001417void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001418 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1419 EmitUint8(0xD9);
1420 EmitOperand(7, dst);
1421}
1422
1423
Ian Rogers2c8f6532011-09-02 17:16:34 -07001424void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001425 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1426 EmitUint8(0xD9);
1427 EmitOperand(5, src);
1428}
1429
1430
Ian Rogers2c8f6532011-09-02 17:16:34 -07001431void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001432 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1433 EmitUint8(0xDF);
1434 EmitOperand(7, dst);
1435}
1436
1437
Ian Rogers2c8f6532011-09-02 17:16:34 -07001438void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001439 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1440 EmitUint8(0xDB);
1441 EmitOperand(3, dst);
1442}
1443
1444
Ian Rogers2c8f6532011-09-02 17:16:34 -07001445void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001446 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1447 EmitUint8(0xDF);
1448 EmitOperand(5, src);
1449}
1450
1451
Roland Levillain0a186012015-04-13 17:00:20 +01001452void X86Assembler::filds(const Address& src) {
1453 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1454 EmitUint8(0xDB);
1455 EmitOperand(0, src);
1456}
1457
1458
Ian Rogers2c8f6532011-09-02 17:16:34 -07001459void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001460 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1461 EmitUint8(0xD9);
1462 EmitUint8(0xF7);
1463}
1464
1465
Ian Rogers2c8f6532011-09-02 17:16:34 -07001466void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001467 CHECK_LT(index.value(), 7);
1468 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1469 EmitUint8(0xDD);
1470 EmitUint8(0xC0 + index.value());
1471}
1472
1473
Ian Rogers2c8f6532011-09-02 17:16:34 -07001474void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001475 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1476 EmitUint8(0xD9);
1477 EmitUint8(0xFE);
1478}
1479
1480
Ian Rogers2c8f6532011-09-02 17:16:34 -07001481void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001482 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1483 EmitUint8(0xD9);
1484 EmitUint8(0xFF);
1485}
1486
1487
Ian Rogers2c8f6532011-09-02 17:16:34 -07001488void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001489 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1490 EmitUint8(0xD9);
1491 EmitUint8(0xF2);
1492}
1493
1494
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001495void X86Assembler::fucompp() {
1496 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1497 EmitUint8(0xDA);
1498 EmitUint8(0xE9);
1499}
1500
1501
1502void X86Assembler::fprem() {
1503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1504 EmitUint8(0xD9);
1505 EmitUint8(0xF8);
1506}
1507
1508
Ian Rogers2c8f6532011-09-02 17:16:34 -07001509void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001510 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1511 EmitUint8(0x87);
1512 EmitRegisterOperand(dst, src);
1513}
1514
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001515
Ian Rogers7caad772012-03-30 01:07:54 -07001516void X86Assembler::xchgl(Register reg, const Address& address) {
1517 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1518 EmitUint8(0x87);
1519 EmitOperand(reg, address);
1520}
1521
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001522
Serguei Katkov3b625932016-05-06 10:24:17 +06001523void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1524 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1525 EmitUint8(0x80);
1526 EmitOperand(7, address);
1527 EmitUint8(imm.value() & 0xFF);
1528}
1529
1530
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001531void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1532 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1533 EmitUint8(0x66);
1534 EmitComplex(7, address, imm);
1535}
1536
1537
Ian Rogers2c8f6532011-09-02 17:16:34 -07001538void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001539 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1540 EmitComplex(7, Operand(reg), imm);
1541}
1542
1543
Ian Rogers2c8f6532011-09-02 17:16:34 -07001544void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001545 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1546 EmitUint8(0x3B);
1547 EmitOperand(reg0, Operand(reg1));
1548}
1549
1550
Ian Rogers2c8f6532011-09-02 17:16:34 -07001551void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001552 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1553 EmitUint8(0x3B);
1554 EmitOperand(reg, address);
1555}
1556
1557
Ian Rogers2c8f6532011-09-02 17:16:34 -07001558void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001559 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1560 EmitUint8(0x03);
1561 EmitRegisterOperand(dst, src);
1562}
1563
1564
Ian Rogers2c8f6532011-09-02 17:16:34 -07001565void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001566 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1567 EmitUint8(0x03);
1568 EmitOperand(reg, address);
1569}
1570
1571
Ian Rogers2c8f6532011-09-02 17:16:34 -07001572void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001573 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1574 EmitUint8(0x39);
1575 EmitOperand(reg, address);
1576}
1577
1578
Ian Rogers2c8f6532011-09-02 17:16:34 -07001579void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1581 EmitComplex(7, address, imm);
1582}
1583
1584
Ian Rogers2c8f6532011-09-02 17:16:34 -07001585void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001586 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1587 EmitUint8(0x85);
1588 EmitRegisterOperand(reg1, reg2);
1589}
1590
1591
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001592void X86Assembler::testl(Register reg, const Address& address) {
1593 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1594 EmitUint8(0x85);
1595 EmitOperand(reg, address);
1596}
1597
1598
Ian Rogers2c8f6532011-09-02 17:16:34 -07001599void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001600 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1601 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1602 // we only test the byte register to keep the encoding short.
1603 if (immediate.is_uint8() && reg < 4) {
1604 // Use zero-extended 8-bit immediate.
1605 if (reg == EAX) {
1606 EmitUint8(0xA8);
1607 } else {
1608 EmitUint8(0xF6);
1609 EmitUint8(0xC0 + reg);
1610 }
1611 EmitUint8(immediate.value() & 0xFF);
1612 } else if (reg == EAX) {
1613 // Use short form if the destination is EAX.
1614 EmitUint8(0xA9);
1615 EmitImmediate(immediate);
1616 } else {
1617 EmitUint8(0xF7);
1618 EmitOperand(0, Operand(reg));
1619 EmitImmediate(immediate);
1620 }
1621}
1622
1623
Vladimir Marko953437b2016-08-24 08:30:46 +00001624void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1625 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1626 EmitUint8(0xF6);
1627 EmitOperand(EAX, dst);
1628 CHECK(imm.is_int8());
1629 EmitUint8(imm.value() & 0xFF);
1630}
1631
1632
1633void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1634 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1635 EmitUint8(0xF7);
1636 EmitOperand(0, dst);
1637 EmitImmediate(imm);
1638}
1639
1640
Ian Rogers2c8f6532011-09-02 17:16:34 -07001641void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001642 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1643 EmitUint8(0x23);
1644 EmitOperand(dst, Operand(src));
1645}
1646
1647
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001648void X86Assembler::andl(Register reg, const Address& address) {
1649 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1650 EmitUint8(0x23);
1651 EmitOperand(reg, address);
1652}
1653
1654
Ian Rogers2c8f6532011-09-02 17:16:34 -07001655void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001656 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1657 EmitComplex(4, Operand(dst), imm);
1658}
1659
1660
Ian Rogers2c8f6532011-09-02 17:16:34 -07001661void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001662 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1663 EmitUint8(0x0B);
1664 EmitOperand(dst, Operand(src));
1665}
1666
1667
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001668void X86Assembler::orl(Register reg, const Address& address) {
1669 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1670 EmitUint8(0x0B);
1671 EmitOperand(reg, address);
1672}
1673
1674
Ian Rogers2c8f6532011-09-02 17:16:34 -07001675void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001676 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1677 EmitComplex(1, Operand(dst), imm);
1678}
1679
1680
Ian Rogers2c8f6532011-09-02 17:16:34 -07001681void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1683 EmitUint8(0x33);
1684 EmitOperand(dst, Operand(src));
1685}
1686
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001687
1688void X86Assembler::xorl(Register reg, const Address& address) {
1689 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1690 EmitUint8(0x33);
1691 EmitOperand(reg, address);
1692}
1693
1694
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01001695void X86Assembler::xorl(Register dst, const Immediate& imm) {
1696 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1697 EmitComplex(6, Operand(dst), imm);
1698}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001699
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001700
Ian Rogers2c8f6532011-09-02 17:16:34 -07001701void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001702 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1703 EmitComplex(0, Operand(reg), imm);
1704}
1705
1706
Ian Rogers2c8f6532011-09-02 17:16:34 -07001707void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001708 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1709 EmitUint8(0x01);
1710 EmitOperand(reg, address);
1711}
1712
1713
Ian Rogers2c8f6532011-09-02 17:16:34 -07001714void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1716 EmitComplex(0, address, imm);
1717}
1718
1719
Ian Rogers2c8f6532011-09-02 17:16:34 -07001720void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001721 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1722 EmitComplex(2, Operand(reg), imm);
1723}
1724
1725
Ian Rogers2c8f6532011-09-02 17:16:34 -07001726void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1728 EmitUint8(0x13);
1729 EmitOperand(dst, Operand(src));
1730}
1731
1732
Ian Rogers2c8f6532011-09-02 17:16:34 -07001733void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001734 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1735 EmitUint8(0x13);
1736 EmitOperand(dst, address);
1737}
1738
1739
Ian Rogers2c8f6532011-09-02 17:16:34 -07001740void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001741 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1742 EmitUint8(0x2B);
1743 EmitOperand(dst, Operand(src));
1744}
1745
1746
Ian Rogers2c8f6532011-09-02 17:16:34 -07001747void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001748 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1749 EmitComplex(5, Operand(reg), imm);
1750}
1751
1752
Ian Rogers2c8f6532011-09-02 17:16:34 -07001753void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1755 EmitUint8(0x2B);
1756 EmitOperand(reg, address);
1757}
1758
1759
Mark Mendell09ed1a32015-03-25 08:30:06 -04001760void X86Assembler::subl(const Address& address, Register reg) {
1761 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1762 EmitUint8(0x29);
1763 EmitOperand(reg, address);
1764}
1765
1766
Ian Rogers2c8f6532011-09-02 17:16:34 -07001767void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001768 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1769 EmitUint8(0x99);
1770}
1771
1772
Ian Rogers2c8f6532011-09-02 17:16:34 -07001773void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001774 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1775 EmitUint8(0xF7);
1776 EmitUint8(0xF8 | reg);
1777}
1778
1779
Ian Rogers2c8f6532011-09-02 17:16:34 -07001780void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1782 EmitUint8(0x0F);
1783 EmitUint8(0xAF);
1784 EmitOperand(dst, Operand(src));
1785}
1786
1787
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001788void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001789 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001790 // See whether imm can be represented as a sign-extended 8bit value.
1791 int32_t v32 = static_cast<int32_t>(imm.value());
1792 if (IsInt<8>(v32)) {
1793 // Sign-extension works.
1794 EmitUint8(0x6B);
1795 EmitOperand(dst, Operand(src));
1796 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
1797 } else {
1798 // Not representable, use full immediate.
1799 EmitUint8(0x69);
1800 EmitOperand(dst, Operand(src));
1801 EmitImmediate(imm);
1802 }
1803}
1804
1805
1806void X86Assembler::imull(Register reg, const Immediate& imm) {
1807 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001808}
1809
1810
Ian Rogers2c8f6532011-09-02 17:16:34 -07001811void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001812 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1813 EmitUint8(0x0F);
1814 EmitUint8(0xAF);
1815 EmitOperand(reg, address);
1816}
1817
1818
Ian Rogers2c8f6532011-09-02 17:16:34 -07001819void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001820 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1821 EmitUint8(0xF7);
1822 EmitOperand(5, Operand(reg));
1823}
1824
1825
Ian Rogers2c8f6532011-09-02 17:16:34 -07001826void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001827 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1828 EmitUint8(0xF7);
1829 EmitOperand(5, address);
1830}
1831
1832
Ian Rogers2c8f6532011-09-02 17:16:34 -07001833void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001834 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1835 EmitUint8(0xF7);
1836 EmitOperand(4, Operand(reg));
1837}
1838
1839
Ian Rogers2c8f6532011-09-02 17:16:34 -07001840void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001841 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1842 EmitUint8(0xF7);
1843 EmitOperand(4, address);
1844}
1845
1846
Ian Rogers2c8f6532011-09-02 17:16:34 -07001847void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001848 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1849 EmitUint8(0x1B);
1850 EmitOperand(dst, Operand(src));
1851}
1852
1853
Ian Rogers2c8f6532011-09-02 17:16:34 -07001854void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001855 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1856 EmitComplex(3, Operand(reg), imm);
1857}
1858
1859
Ian Rogers2c8f6532011-09-02 17:16:34 -07001860void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001861 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1862 EmitUint8(0x1B);
1863 EmitOperand(dst, address);
1864}
1865
1866
Mark Mendell09ed1a32015-03-25 08:30:06 -04001867void X86Assembler::sbbl(const Address& address, Register src) {
1868 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1869 EmitUint8(0x19);
1870 EmitOperand(src, address);
1871}
1872
1873
Ian Rogers2c8f6532011-09-02 17:16:34 -07001874void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001875 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1876 EmitUint8(0x40 + reg);
1877}
1878
1879
Ian Rogers2c8f6532011-09-02 17:16:34 -07001880void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001881 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1882 EmitUint8(0xFF);
1883 EmitOperand(0, address);
1884}
1885
1886
Ian Rogers2c8f6532011-09-02 17:16:34 -07001887void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001888 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1889 EmitUint8(0x48 + reg);
1890}
1891
1892
Ian Rogers2c8f6532011-09-02 17:16:34 -07001893void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001894 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1895 EmitUint8(0xFF);
1896 EmitOperand(1, address);
1897}
1898
1899
Ian Rogers2c8f6532011-09-02 17:16:34 -07001900void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001901 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001902}
1903
1904
Ian Rogers2c8f6532011-09-02 17:16:34 -07001905void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001906 EmitGenericShift(4, Operand(operand), shifter);
1907}
1908
1909
1910void X86Assembler::shll(const Address& address, const Immediate& imm) {
1911 EmitGenericShift(4, address, imm);
1912}
1913
1914
1915void X86Assembler::shll(const Address& address, Register shifter) {
1916 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001917}
1918
1919
Ian Rogers2c8f6532011-09-02 17:16:34 -07001920void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001921 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001922}
1923
1924
Ian Rogers2c8f6532011-09-02 17:16:34 -07001925void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001926 EmitGenericShift(5, Operand(operand), shifter);
1927}
1928
1929
1930void X86Assembler::shrl(const Address& address, const Immediate& imm) {
1931 EmitGenericShift(5, address, imm);
1932}
1933
1934
1935void X86Assembler::shrl(const Address& address, Register shifter) {
1936 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001937}
1938
1939
Ian Rogers2c8f6532011-09-02 17:16:34 -07001940void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001941 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001942}
1943
1944
Ian Rogers2c8f6532011-09-02 17:16:34 -07001945void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001946 EmitGenericShift(7, Operand(operand), shifter);
1947}
1948
1949
1950void X86Assembler::sarl(const Address& address, const Immediate& imm) {
1951 EmitGenericShift(7, address, imm);
1952}
1953
1954
1955void X86Assembler::sarl(const Address& address, Register shifter) {
1956 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001957}
1958
1959
Calin Juravle9aec02f2014-11-18 23:06:35 +00001960void X86Assembler::shld(Register dst, Register src, Register shifter) {
1961 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1963 EmitUint8(0x0F);
1964 EmitUint8(0xA5);
1965 EmitRegisterOperand(src, dst);
1966}
1967
1968
Mark P Mendell73945692015-04-29 14:56:17 +00001969void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
1970 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1971 EmitUint8(0x0F);
1972 EmitUint8(0xA4);
1973 EmitRegisterOperand(src, dst);
1974 EmitUint8(imm.value() & 0xFF);
1975}
1976
1977
Calin Juravle9aec02f2014-11-18 23:06:35 +00001978void X86Assembler::shrd(Register dst, Register src, Register shifter) {
1979 DCHECK_EQ(ECX, shifter);
1980 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1981 EmitUint8(0x0F);
1982 EmitUint8(0xAD);
1983 EmitRegisterOperand(src, dst);
1984}
1985
1986
Mark P Mendell73945692015-04-29 14:56:17 +00001987void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
1988 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1989 EmitUint8(0x0F);
1990 EmitUint8(0xAC);
1991 EmitRegisterOperand(src, dst);
1992 EmitUint8(imm.value() & 0xFF);
1993}
1994
1995
Mark Mendellbcee0922015-09-15 21:45:01 -04001996void X86Assembler::roll(Register reg, const Immediate& imm) {
1997 EmitGenericShift(0, Operand(reg), imm);
1998}
1999
2000
2001void X86Assembler::roll(Register operand, Register shifter) {
2002 EmitGenericShift(0, Operand(operand), shifter);
2003}
2004
2005
2006void X86Assembler::rorl(Register reg, const Immediate& imm) {
2007 EmitGenericShift(1, Operand(reg), imm);
2008}
2009
2010
2011void X86Assembler::rorl(Register operand, Register shifter) {
2012 EmitGenericShift(1, Operand(operand), shifter);
2013}
2014
2015
Ian Rogers2c8f6532011-09-02 17:16:34 -07002016void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002017 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2018 EmitUint8(0xF7);
2019 EmitOperand(3, Operand(reg));
2020}
2021
2022
Ian Rogers2c8f6532011-09-02 17:16:34 -07002023void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002024 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2025 EmitUint8(0xF7);
2026 EmitUint8(0xD0 | reg);
2027}
2028
2029
Ian Rogers2c8f6532011-09-02 17:16:34 -07002030void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002031 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2032 EmitUint8(0xC8);
2033 CHECK(imm.is_uint16());
2034 EmitUint8(imm.value() & 0xFF);
2035 EmitUint8((imm.value() >> 8) & 0xFF);
2036 EmitUint8(0x00);
2037}
2038
2039
Ian Rogers2c8f6532011-09-02 17:16:34 -07002040void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002041 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2042 EmitUint8(0xC9);
2043}
2044
2045
Ian Rogers2c8f6532011-09-02 17:16:34 -07002046void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002047 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2048 EmitUint8(0xC3);
2049}
2050
2051
Ian Rogers2c8f6532011-09-02 17:16:34 -07002052void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002053 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2054 EmitUint8(0xC2);
2055 CHECK(imm.is_uint16());
2056 EmitUint8(imm.value() & 0xFF);
2057 EmitUint8((imm.value() >> 8) & 0xFF);
2058}
2059
2060
2061
Ian Rogers2c8f6532011-09-02 17:16:34 -07002062void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002063 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2064 EmitUint8(0x90);
2065}
2066
2067
Ian Rogers2c8f6532011-09-02 17:16:34 -07002068void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2070 EmitUint8(0xCC);
2071}
2072
2073
Ian Rogers2c8f6532011-09-02 17:16:34 -07002074void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2076 EmitUint8(0xF4);
2077}
2078
2079
Ian Rogers2c8f6532011-09-02 17:16:34 -07002080void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002081 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2082 if (label->IsBound()) {
2083 static const int kShortSize = 2;
2084 static const int kLongSize = 6;
2085 int offset = label->Position() - buffer_.Size();
2086 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002087 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002088 EmitUint8(0x70 + condition);
2089 EmitUint8((offset - kShortSize) & 0xFF);
2090 } else {
2091 EmitUint8(0x0F);
2092 EmitUint8(0x80 + condition);
2093 EmitInt32(offset - kLongSize);
2094 }
2095 } else {
2096 EmitUint8(0x0F);
2097 EmitUint8(0x80 + condition);
2098 EmitLabelLink(label);
2099 }
2100}
2101
2102
Mark Mendell73f455e2015-08-21 09:30:05 -04002103void X86Assembler::j(Condition condition, NearLabel* label) {
2104 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2105 if (label->IsBound()) {
2106 static const int kShortSize = 2;
2107 int offset = label->Position() - buffer_.Size();
2108 CHECK_LE(offset, 0);
2109 CHECK(IsInt<8>(offset - kShortSize));
2110 EmitUint8(0x70 + condition);
2111 EmitUint8((offset - kShortSize) & 0xFF);
2112 } else {
2113 EmitUint8(0x70 + condition);
2114 EmitLabelLink(label);
2115 }
2116}
2117
2118
2119void X86Assembler::jecxz(NearLabel* label) {
2120 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2121 if (label->IsBound()) {
2122 static const int kShortSize = 2;
2123 int offset = label->Position() - buffer_.Size();
2124 CHECK_LE(offset, 0);
2125 CHECK(IsInt<8>(offset - kShortSize));
2126 EmitUint8(0xE3);
2127 EmitUint8((offset - kShortSize) & 0xFF);
2128 } else {
2129 EmitUint8(0xE3);
2130 EmitLabelLink(label);
2131 }
2132}
2133
2134
Ian Rogers2c8f6532011-09-02 17:16:34 -07002135void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002136 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2137 EmitUint8(0xFF);
2138 EmitRegisterOperand(4, reg);
2139}
2140
Ian Rogers7caad772012-03-30 01:07:54 -07002141void X86Assembler::jmp(const Address& address) {
2142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2143 EmitUint8(0xFF);
2144 EmitOperand(4, address);
2145}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002146
Ian Rogers2c8f6532011-09-02 17:16:34 -07002147void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2149 if (label->IsBound()) {
2150 static const int kShortSize = 2;
2151 static const int kLongSize = 5;
2152 int offset = label->Position() - buffer_.Size();
2153 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002154 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002155 EmitUint8(0xEB);
2156 EmitUint8((offset - kShortSize) & 0xFF);
2157 } else {
2158 EmitUint8(0xE9);
2159 EmitInt32(offset - kLongSize);
2160 }
2161 } else {
2162 EmitUint8(0xE9);
2163 EmitLabelLink(label);
2164 }
2165}
2166
2167
Mark Mendell73f455e2015-08-21 09:30:05 -04002168void X86Assembler::jmp(NearLabel* label) {
2169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2170 if (label->IsBound()) {
2171 static const int kShortSize = 2;
2172 int offset = label->Position() - buffer_.Size();
2173 CHECK_LE(offset, 0);
2174 CHECK(IsInt<8>(offset - kShortSize));
2175 EmitUint8(0xEB);
2176 EmitUint8((offset - kShortSize) & 0xFF);
2177 } else {
2178 EmitUint8(0xEB);
2179 EmitLabelLink(label);
2180 }
2181}
2182
2183
jessicahandojob03d6402016-09-07 12:16:53 -07002184void X86Assembler::repne_scasb() {
2185 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2186 EmitUint8(0xF2);
2187 EmitUint8(0xAE);
2188}
2189
2190
Andreas Gampe21030dd2015-05-07 14:46:15 -07002191void X86Assembler::repne_scasw() {
2192 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2193 EmitUint8(0x66);
2194 EmitUint8(0xF2);
2195 EmitUint8(0xAF);
2196}
2197
2198
jessicahandojob03d6402016-09-07 12:16:53 -07002199void X86Assembler::repe_cmpsb() {
2200 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2201 EmitUint8(0xF2);
2202 EmitUint8(0xA6);
2203}
2204
2205
agicsaki71311f82015-07-27 11:34:13 -07002206void X86Assembler::repe_cmpsw() {
2207 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2208 EmitUint8(0x66);
2209 EmitUint8(0xF3);
2210 EmitUint8(0xA7);
2211}
2212
2213
agicsaki970abfb2015-07-31 10:31:14 -07002214void X86Assembler::repe_cmpsl() {
2215 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2216 EmitUint8(0xF3);
2217 EmitUint8(0xA7);
2218}
2219
2220
jessicahandojob03d6402016-09-07 12:16:53 -07002221void X86Assembler::rep_movsb() {
2222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2223 EmitUint8(0xF3);
2224 EmitUint8(0xA4);
2225}
2226
2227
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002228void X86Assembler::rep_movsw() {
2229 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2230 EmitUint8(0x66);
2231 EmitUint8(0xF3);
2232 EmitUint8(0xA5);
2233}
2234
2235
Ian Rogers2c8f6532011-09-02 17:16:34 -07002236X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002237 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2238 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002239 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002240}
2241
2242
Ian Rogers2c8f6532011-09-02 17:16:34 -07002243void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002244 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2245 EmitUint8(0x0F);
2246 EmitUint8(0xB1);
2247 EmitOperand(reg, address);
2248}
2249
Mark Mendell58d25fd2015-04-03 14:52:31 -04002250
2251void X86Assembler::cmpxchg8b(const Address& address) {
2252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2253 EmitUint8(0x0F);
2254 EmitUint8(0xC7);
2255 EmitOperand(1, address);
2256}
2257
2258
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002259void X86Assembler::mfence() {
2260 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2261 EmitUint8(0x0F);
2262 EmitUint8(0xAE);
2263 EmitUint8(0xF0);
2264}
2265
Ian Rogers2c8f6532011-09-02 17:16:34 -07002266X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002267 // TODO: fs is a prefix and not an instruction
2268 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2269 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002270 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002271}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002272
Ian Rogersbefbd572014-03-06 01:13:39 -08002273X86Assembler* X86Assembler::gs() {
2274 // TODO: fs is a prefix and not an instruction
2275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2276 EmitUint8(0x65);
2277 return this;
2278}
2279
Ian Rogers2c8f6532011-09-02 17:16:34 -07002280void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002281 int value = imm.value();
2282 if (value > 0) {
2283 if (value == 1) {
2284 incl(reg);
2285 } else if (value != 0) {
2286 addl(reg, imm);
2287 }
2288 } else if (value < 0) {
2289 value = -value;
2290 if (value == 1) {
2291 decl(reg);
2292 } else if (value != 0) {
2293 subl(reg, Immediate(value));
2294 }
2295 }
2296}
2297
2298
Roland Levillain647b9ed2014-11-27 12:06:00 +00002299void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2300 // TODO: Need to have a code constants table.
2301 pushl(Immediate(High32Bits(value)));
2302 pushl(Immediate(Low32Bits(value)));
2303 movsd(dst, Address(ESP, 0));
2304 addl(ESP, Immediate(2 * sizeof(int32_t)));
2305}
2306
2307
Ian Rogers2c8f6532011-09-02 17:16:34 -07002308void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002309 // TODO: Need to have a code constants table.
2310 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002311 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002312}
2313
2314
Ian Rogers2c8f6532011-09-02 17:16:34 -07002315void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002316 CHECK(IsPowerOfTwo(alignment));
2317 // Emit nop instruction until the real position is aligned.
2318 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2319 nop();
2320 }
2321}
2322
2323
Ian Rogers2c8f6532011-09-02 17:16:34 -07002324void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002325 int bound = buffer_.Size();
2326 CHECK(!label->IsBound()); // Labels can only be bound once.
2327 while (label->IsLinked()) {
2328 int position = label->LinkPosition();
2329 int next = buffer_.Load<int32_t>(position);
2330 buffer_.Store<int32_t>(position, bound - (position + 4));
2331 label->position_ = next;
2332 }
2333 label->BindTo(bound);
2334}
2335
2336
Mark Mendell73f455e2015-08-21 09:30:05 -04002337void X86Assembler::Bind(NearLabel* label) {
2338 int bound = buffer_.Size();
2339 CHECK(!label->IsBound()); // Labels can only be bound once.
2340 while (label->IsLinked()) {
2341 int position = label->LinkPosition();
2342 uint8_t delta = buffer_.Load<uint8_t>(position);
2343 int offset = bound - (position + 1);
2344 CHECK(IsInt<8>(offset));
2345 buffer_.Store<int8_t>(position, offset);
2346 label->position_ = delta != 0u ? label->position_ - delta : 0;
2347 }
2348 label->BindTo(bound);
2349}
2350
2351
Ian Rogers44fb0d02012-03-23 16:46:24 -07002352void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2353 CHECK_GE(reg_or_opcode, 0);
2354 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002355 const int length = operand.length_;
2356 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002357 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002358 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002359 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002360 // Emit the rest of the encoded operand.
2361 for (int i = 1; i < length; i++) {
2362 EmitUint8(operand.encoding_[i]);
2363 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002364 AssemblerFixup* fixup = operand.GetFixup();
2365 if (fixup != nullptr) {
2366 EmitFixup(fixup);
2367 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002368}
2369
2370
Ian Rogers2c8f6532011-09-02 17:16:34 -07002371void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002372 EmitInt32(imm.value());
2373}
2374
2375
Ian Rogers44fb0d02012-03-23 16:46:24 -07002376void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002377 const Operand& operand,
2378 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002379 CHECK_GE(reg_or_opcode, 0);
2380 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002381 if (immediate.is_int8()) {
2382 // Use sign-extended 8-bit immediate.
2383 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002384 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002385 EmitUint8(immediate.value() & 0xFF);
2386 } else if (operand.IsRegister(EAX)) {
2387 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002388 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002389 EmitImmediate(immediate);
2390 } else {
2391 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002392 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002393 EmitImmediate(immediate);
2394 }
2395}
2396
2397
Ian Rogers2c8f6532011-09-02 17:16:34 -07002398void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002399 if (label->IsBound()) {
2400 int offset = label->Position() - buffer_.Size();
2401 CHECK_LE(offset, 0);
2402 EmitInt32(offset - instruction_size);
2403 } else {
2404 EmitLabelLink(label);
2405 }
2406}
2407
2408
Ian Rogers2c8f6532011-09-02 17:16:34 -07002409void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002410 CHECK(!label->IsBound());
2411 int position = buffer_.Size();
2412 EmitInt32(label->position_);
2413 label->LinkTo(position);
2414}
2415
2416
Mark Mendell73f455e2015-08-21 09:30:05 -04002417void X86Assembler::EmitLabelLink(NearLabel* label) {
2418 CHECK(!label->IsBound());
2419 int position = buffer_.Size();
2420 if (label->IsLinked()) {
2421 // Save the delta in the byte that we have to play with.
2422 uint32_t delta = position - label->LinkPosition();
2423 CHECK(IsUint<8>(delta));
2424 EmitUint8(delta & 0xFF);
2425 } else {
2426 EmitUint8(0);
2427 }
2428 label->LinkTo(position);
2429}
2430
2431
Ian Rogers44fb0d02012-03-23 16:46:24 -07002432void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002433 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002434 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002435 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2436 CHECK(imm.is_int8());
2437 if (imm.value() == 1) {
2438 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002439 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002440 } else {
2441 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002442 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002443 EmitUint8(imm.value() & 0xFF);
2444 }
2445}
2446
2447
Ian Rogers44fb0d02012-03-23 16:46:24 -07002448void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002449 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002450 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002451 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2452 CHECK_EQ(shifter, ECX);
2453 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002454 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002455}
2456
Mark Mendell0616ae02015-04-17 12:49:27 -04002457void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002458 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002459 // Generate the data for the literal area.
2460 for (size_t i = 0, e = area.size(); i < e; i++) {
2461 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2462 EmitInt32(area[i]);
2463 }
2464}
2465
Mark Mendell805b3b52015-09-18 14:10:29 -04002466size_t ConstantArea::AppendInt32(int32_t v) {
2467 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002468 buffer_.push_back(v);
2469 return result;
2470}
2471
Mark Mendell805b3b52015-09-18 14:10:29 -04002472size_t ConstantArea::AddInt32(int32_t v) {
2473 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2474 if (v == buffer_[i]) {
2475 return i * elem_size_;
2476 }
2477 }
2478
2479 // Didn't match anything.
2480 return AppendInt32(v);
2481}
2482
2483size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002484 int32_t v_low = Low32Bits(v);
2485 int32_t v_high = High32Bits(v);
2486 if (buffer_.size() > 1) {
2487 // Ensure we don't pass the end of the buffer.
2488 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2489 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002490 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002491 }
2492 }
2493 }
2494
2495 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002496 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002497 buffer_.push_back(v_low);
2498 buffer_.push_back(v_high);
2499 return result;
2500}
2501
Mark Mendell805b3b52015-09-18 14:10:29 -04002502size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002503 // Treat the value as a 64-bit integer value.
2504 return AddInt64(bit_cast<int64_t, double>(v));
2505}
2506
Mark Mendell805b3b52015-09-18 14:10:29 -04002507size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002508 // Treat the value as a 32-bit integer value.
2509 return AddInt32(bit_cast<int32_t, float>(v));
2510}
2511
Ian Rogers2c8f6532011-09-02 17:16:34 -07002512} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002513} // namespace art