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Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Aart Bikc7782262017-01-13 16:20:08 -0800353void X86Assembler::movaps(XmmRegister dst, const Address& src) {
354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0x0F);
356 EmitUint8(0x28);
357 EmitOperand(dst, src);
358}
359
360
361void X86Assembler::movups(XmmRegister dst, const Address& src) {
362 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363 EmitUint8(0x0F);
364 EmitUint8(0x10);
365 EmitOperand(dst, src);
366}
367
368
369void X86Assembler::movaps(const Address& dst, XmmRegister src) {
370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
371 EmitUint8(0x0F);
372 EmitUint8(0x29);
373 EmitOperand(src, dst);
374}
375
376
377void X86Assembler::movups(const Address& dst, XmmRegister src) {
378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
379 EmitUint8(0x0F);
380 EmitUint8(0x11);
381 EmitOperand(src, dst);
382}
383
384
Ian Rogers2c8f6532011-09-02 17:16:34 -0700385void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
387 EmitUint8(0xF3);
388 EmitUint8(0x0F);
389 EmitUint8(0x10);
390 EmitOperand(dst, src);
391}
392
393
Ian Rogers2c8f6532011-09-02 17:16:34 -0700394void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
396 EmitUint8(0xF3);
397 EmitUint8(0x0F);
398 EmitUint8(0x11);
399 EmitOperand(src, dst);
400}
401
402
Ian Rogers2c8f6532011-09-02 17:16:34 -0700403void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700404 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
405 EmitUint8(0xF3);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitXmmRegisterOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0x66);
415 EmitUint8(0x0F);
416 EmitUint8(0x6E);
417 EmitOperand(dst, Operand(src));
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0x66);
424 EmitUint8(0x0F);
425 EmitUint8(0x7E);
426 EmitOperand(src, Operand(dst));
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x58);
435 EmitXmmRegisterOperand(dst, src);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0xF3);
442 EmitUint8(0x0F);
443 EmitUint8(0x58);
444 EmitOperand(dst, src);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0xF3);
451 EmitUint8(0x0F);
452 EmitUint8(0x5C);
453 EmitXmmRegisterOperand(dst, src);
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x5C);
462 EmitOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x59);
471 EmitXmmRegisterOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x59);
480 EmitOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5E);
489 EmitXmmRegisterOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x5E);
498 EmitOperand(dst, src);
499}
500
501
Aart Bikc7782262017-01-13 16:20:08 -0800502void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0x0F);
505 EmitUint8(0x58);
506 EmitXmmRegisterOperand(dst, src);
507}
508
509
510void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
512 EmitUint8(0x0F);
513 EmitUint8(0x5C);
514 EmitXmmRegisterOperand(dst, src);
515}
516
517
518void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x0F);
521 EmitUint8(0x59);
522 EmitXmmRegisterOperand(dst, src);
523}
524
525
526void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528 EmitUint8(0x0F);
529 EmitUint8(0x5E);
530 EmitXmmRegisterOperand(dst, src);
531}
532
533
534void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
536 EmitUint8(0x66);
537 EmitUint8(0x0F);
538 EmitUint8(0x28);
539 EmitXmmRegisterOperand(dst, src);
540}
541
542
543void X86Assembler::movapd(XmmRegister dst, const Address& src) {
544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
545 EmitUint8(0x66);
546 EmitUint8(0x0F);
547 EmitUint8(0x28);
548 EmitOperand(dst, src);
549}
550
551
552void X86Assembler::movupd(XmmRegister dst, const Address& src) {
553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
554 EmitUint8(0x66);
555 EmitUint8(0x0F);
556 EmitUint8(0x10);
557 EmitOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(const Address& dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x29);
566 EmitOperand(src, dst);
567}
568
569
570void X86Assembler::movupd(const Address& dst, XmmRegister src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x11);
575 EmitOperand(src, dst);
576}
577
578
Ian Rogers2c8f6532011-09-02 17:16:34 -0700579void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0xD9);
582 EmitOperand(0, src);
583}
584
585
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500586void X86Assembler::fsts(const Address& dst) {
587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588 EmitUint8(0xD9);
589 EmitOperand(2, dst);
590}
591
592
Ian Rogers2c8f6532011-09-02 17:16:34 -0700593void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
595 EmitUint8(0xD9);
596 EmitOperand(3, dst);
597}
598
599
Ian Rogers2c8f6532011-09-02 17:16:34 -0700600void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF2);
603 EmitUint8(0x0F);
604 EmitUint8(0x10);
605 EmitOperand(dst, src);
606}
607
608
Ian Rogers2c8f6532011-09-02 17:16:34 -0700609void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0xF2);
612 EmitUint8(0x0F);
613 EmitUint8(0x11);
614 EmitOperand(src, dst);
615}
616
617
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0xF2);
621 EmitUint8(0x0F);
622 EmitUint8(0x11);
623 EmitXmmRegisterOperand(src, dst);
624}
625
626
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000627void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0x66);
630 EmitUint8(0x0F);
631 EmitUint8(0x16);
632 EmitOperand(dst, src);
633}
634
635
636void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0x66);
639 EmitUint8(0x0F);
640 EmitUint8(0x17);
641 EmitOperand(src, dst);
642}
643
644
Ian Rogers2c8f6532011-09-02 17:16:34 -0700645void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF2);
648 EmitUint8(0x0F);
649 EmitUint8(0x58);
650 EmitXmmRegisterOperand(dst, src);
651}
652
653
Ian Rogers2c8f6532011-09-02 17:16:34 -0700654void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0xF2);
657 EmitUint8(0x0F);
658 EmitUint8(0x58);
659 EmitOperand(dst, src);
660}
661
662
Ian Rogers2c8f6532011-09-02 17:16:34 -0700663void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0xF2);
666 EmitUint8(0x0F);
667 EmitUint8(0x5C);
668 EmitXmmRegisterOperand(dst, src);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF2);
675 EmitUint8(0x0F);
676 EmitUint8(0x5C);
677 EmitOperand(dst, src);
678}
679
680
Ian Rogers2c8f6532011-09-02 17:16:34 -0700681void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF2);
684 EmitUint8(0x0F);
685 EmitUint8(0x59);
686 EmitXmmRegisterOperand(dst, src);
687}
688
689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF2);
693 EmitUint8(0x0F);
694 EmitUint8(0x59);
695 EmitOperand(dst, src);
696}
697
698
Ian Rogers2c8f6532011-09-02 17:16:34 -0700699void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0xF2);
702 EmitUint8(0x0F);
703 EmitUint8(0x5E);
704 EmitXmmRegisterOperand(dst, src);
705}
706
707
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
710 EmitUint8(0xF2);
711 EmitUint8(0x0F);
712 EmitUint8(0x5E);
713 EmitOperand(dst, src);
714}
715
716
Aart Bikc7782262017-01-13 16:20:08 -0800717void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
719 EmitUint8(0x66);
720 EmitUint8(0x0F);
721 EmitUint8(0x58);
722 EmitXmmRegisterOperand(dst, src);
723}
724
725
726void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
728 EmitUint8(0x66);
729 EmitUint8(0x0F);
730 EmitUint8(0x5C);
731 EmitXmmRegisterOperand(dst, src);
732}
733
734
735void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
737 EmitUint8(0x66);
738 EmitUint8(0x0F);
739 EmitUint8(0x59);
740 EmitXmmRegisterOperand(dst, src);
741}
742
743
744void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
746 EmitUint8(0x66);
747 EmitUint8(0x0F);
748 EmitUint8(0x5E);
749 EmitXmmRegisterOperand(dst, src);
750}
751
752
Aart Bik68555e92017-02-13 14:28:45 -0800753void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755 EmitUint8(0x66);
756 EmitUint8(0x0F);
757 EmitUint8(0x6F);
758 EmitXmmRegisterOperand(dst, src);
759}
760
761
762void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
764 EmitUint8(0x66);
765 EmitUint8(0x0F);
766 EmitUint8(0x6F);
767 EmitOperand(dst, src);
768}
769
770
771void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
773 EmitUint8(0xF3);
774 EmitUint8(0x0F);
775 EmitUint8(0x6F);
776 EmitOperand(dst, src);
777}
778
779
780void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
782 EmitUint8(0x66);
783 EmitUint8(0x0F);
784 EmitUint8(0x7F);
785 EmitOperand(src, dst);
786}
787
788
789void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791 EmitUint8(0xF3);
792 EmitUint8(0x0F);
793 EmitUint8(0x7F);
794 EmitOperand(src, dst);
795}
796
797
Aart Bike69d7a92017-02-17 11:48:23 -0800798void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
799 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
800 EmitUint8(0x66);
801 EmitUint8(0x0F);
802 EmitUint8(0xFC);
803 EmitXmmRegisterOperand(dst, src);
804}
805
806
807void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
809 EmitUint8(0x66);
810 EmitUint8(0x0F);
811 EmitUint8(0xF8);
812 EmitXmmRegisterOperand(dst, src);
813}
814
815
816void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
818 EmitUint8(0x66);
819 EmitUint8(0x0F);
820 EmitUint8(0xFD);
821 EmitXmmRegisterOperand(dst, src);
822}
823
824
825void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
826 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827 EmitUint8(0x66);
828 EmitUint8(0x0F);
829 EmitUint8(0xF9);
830 EmitXmmRegisterOperand(dst, src);
831}
832
833
834void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836 EmitUint8(0x66);
837 EmitUint8(0x0F);
838 EmitUint8(0xD5);
839 EmitXmmRegisterOperand(dst, src);
840}
841
842
Aart Bik68555e92017-02-13 14:28:45 -0800843void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
845 EmitUint8(0x66);
846 EmitUint8(0x0F);
847 EmitUint8(0xFE);
848 EmitXmmRegisterOperand(dst, src);
849}
850
851
852void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
854 EmitUint8(0x66);
855 EmitUint8(0x0F);
856 EmitUint8(0xFA);
857 EmitXmmRegisterOperand(dst, src);
858}
859
860
861void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0x38);
866 EmitUint8(0x40);
867 EmitXmmRegisterOperand(dst, src);
868}
869
870
Aart Bike69d7a92017-02-17 11:48:23 -0800871void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
872 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
873 EmitUint8(0x66);
874 EmitUint8(0x0F);
875 EmitUint8(0xD4);
876 EmitXmmRegisterOperand(dst, src);
877}
878
879
880void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
881 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
882 EmitUint8(0x66);
883 EmitUint8(0x0F);
884 EmitUint8(0xFB);
885 EmitXmmRegisterOperand(dst, src);
886}
887
888
Ian Rogers2c8f6532011-09-02 17:16:34 -0700889void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700890 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
891 EmitUint8(0xF3);
892 EmitUint8(0x0F);
893 EmitUint8(0x2A);
894 EmitOperand(dst, Operand(src));
895}
896
897
Ian Rogers2c8f6532011-09-02 17:16:34 -0700898void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0xF2);
901 EmitUint8(0x0F);
902 EmitUint8(0x2A);
903 EmitOperand(dst, Operand(src));
904}
905
906
Ian Rogers2c8f6532011-09-02 17:16:34 -0700907void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
909 EmitUint8(0xF3);
910 EmitUint8(0x0F);
911 EmitUint8(0x2D);
912 EmitXmmRegisterOperand(dst, src);
913}
914
915
Ian Rogers2c8f6532011-09-02 17:16:34 -0700916void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
918 EmitUint8(0xF3);
919 EmitUint8(0x0F);
920 EmitUint8(0x5A);
921 EmitXmmRegisterOperand(dst, src);
922}
923
924
Ian Rogers2c8f6532011-09-02 17:16:34 -0700925void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700926 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
927 EmitUint8(0xF2);
928 EmitUint8(0x0F);
929 EmitUint8(0x2D);
930 EmitXmmRegisterOperand(dst, src);
931}
932
933
Ian Rogers2c8f6532011-09-02 17:16:34 -0700934void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936 EmitUint8(0xF3);
937 EmitUint8(0x0F);
938 EmitUint8(0x2C);
939 EmitXmmRegisterOperand(dst, src);
940}
941
942
Ian Rogers2c8f6532011-09-02 17:16:34 -0700943void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
945 EmitUint8(0xF2);
946 EmitUint8(0x0F);
947 EmitUint8(0x2C);
948 EmitXmmRegisterOperand(dst, src);
949}
950
951
Ian Rogers2c8f6532011-09-02 17:16:34 -0700952void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954 EmitUint8(0xF2);
955 EmitUint8(0x0F);
956 EmitUint8(0x5A);
957 EmitXmmRegisterOperand(dst, src);
958}
959
960
Aart Bik3ae3b592017-02-24 14:09:15 -0800961void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0x0F);
964 EmitUint8(0x5B);
965 EmitXmmRegisterOperand(dst, src);
966}
967
968
Ian Rogers2c8f6532011-09-02 17:16:34 -0700969void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700970 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
971 EmitUint8(0xF3);
972 EmitUint8(0x0F);
973 EmitUint8(0xE6);
974 EmitXmmRegisterOperand(dst, src);
975}
976
977
Ian Rogers2c8f6532011-09-02 17:16:34 -0700978void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700979 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
980 EmitUint8(0x0F);
981 EmitUint8(0x2F);
982 EmitXmmRegisterOperand(a, b);
983}
984
985
Aart Bik18ba1212016-08-01 14:11:20 -0700986void X86Assembler::comiss(XmmRegister a, const Address& b) {
987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
988 EmitUint8(0x0F);
989 EmitUint8(0x2F);
990 EmitOperand(a, b);
991}
992
993
Ian Rogers2c8f6532011-09-02 17:16:34 -0700994void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700995 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
996 EmitUint8(0x66);
997 EmitUint8(0x0F);
998 EmitUint8(0x2F);
999 EmitXmmRegisterOperand(a, b);
1000}
1001
1002
Aart Bik18ba1212016-08-01 14:11:20 -07001003void X86Assembler::comisd(XmmRegister a, const Address& b) {
1004 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1005 EmitUint8(0x66);
1006 EmitUint8(0x0F);
1007 EmitUint8(0x2F);
1008 EmitOperand(a, b);
1009}
1010
1011
Calin Juravleddb7df22014-11-25 20:56:51 +00001012void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1013 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1014 EmitUint8(0x0F);
1015 EmitUint8(0x2E);
1016 EmitXmmRegisterOperand(a, b);
1017}
1018
1019
Mark Mendell9f51f262015-10-30 09:21:37 -04001020void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1022 EmitUint8(0x0F);
1023 EmitUint8(0x2E);
1024 EmitOperand(a, b);
1025}
1026
1027
Calin Juravleddb7df22014-11-25 20:56:51 +00001028void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1029 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1030 EmitUint8(0x66);
1031 EmitUint8(0x0F);
1032 EmitUint8(0x2E);
1033 EmitXmmRegisterOperand(a, b);
1034}
1035
1036
Mark Mendell9f51f262015-10-30 09:21:37 -04001037void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1038 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1039 EmitUint8(0x66);
1040 EmitUint8(0x0F);
1041 EmitUint8(0x2E);
1042 EmitOperand(a, b);
1043}
1044
1045
Mark Mendellfb8d2792015-03-31 22:16:59 -04001046void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1047 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1048 EmitUint8(0x66);
1049 EmitUint8(0x0F);
1050 EmitUint8(0x3A);
1051 EmitUint8(0x0B);
1052 EmitXmmRegisterOperand(dst, src);
1053 EmitUint8(imm.value());
1054}
1055
1056
1057void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1058 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1059 EmitUint8(0x66);
1060 EmitUint8(0x0F);
1061 EmitUint8(0x3A);
1062 EmitUint8(0x0A);
1063 EmitXmmRegisterOperand(dst, src);
1064 EmitUint8(imm.value());
1065}
1066
1067
Ian Rogers2c8f6532011-09-02 17:16:34 -07001068void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1070 EmitUint8(0xF2);
1071 EmitUint8(0x0F);
1072 EmitUint8(0x51);
1073 EmitXmmRegisterOperand(dst, src);
1074}
1075
1076
Ian Rogers2c8f6532011-09-02 17:16:34 -07001077void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001078 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1079 EmitUint8(0xF3);
1080 EmitUint8(0x0F);
1081 EmitUint8(0x51);
1082 EmitXmmRegisterOperand(dst, src);
1083}
1084
1085
Ian Rogers2c8f6532011-09-02 17:16:34 -07001086void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001087 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1088 EmitUint8(0x66);
1089 EmitUint8(0x0F);
1090 EmitUint8(0x57);
1091 EmitOperand(dst, src);
1092}
1093
1094
Ian Rogers2c8f6532011-09-02 17:16:34 -07001095void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1097 EmitUint8(0x66);
1098 EmitUint8(0x0F);
1099 EmitUint8(0x57);
1100 EmitXmmRegisterOperand(dst, src);
1101}
1102
1103
Aart Bik68555e92017-02-13 14:28:45 -08001104void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001105 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1106 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001107 EmitUint8(0x57);
1108 EmitOperand(dst, src);
1109}
1110
1111
1112void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1113 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1114 EmitUint8(0x0F);
1115 EmitUint8(0x57);
1116 EmitXmmRegisterOperand(dst, src);
1117}
1118
1119
1120void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1122 EmitUint8(0x66);
1123 EmitUint8(0x0F);
1124 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001125 EmitXmmRegisterOperand(dst, src);
1126}
1127
1128
1129void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131 EmitUint8(0x66);
1132 EmitUint8(0x0F);
1133 EmitUint8(0x54);
1134 EmitXmmRegisterOperand(dst, src);
1135}
1136
1137
Aart Bik68555e92017-02-13 14:28:45 -08001138void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001139 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1140 EmitUint8(0x66);
1141 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001142 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001143 EmitOperand(dst, src);
1144}
1145
1146
Aart Bik68555e92017-02-13 14:28:45 -08001147void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1149 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001150 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001151 EmitXmmRegisterOperand(dst, src);
1152}
1153
1154
Mark Mendell09ed1a32015-03-25 08:30:06 -04001155void X86Assembler::andps(XmmRegister dst, const Address& src) {
1156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1157 EmitUint8(0x0F);
1158 EmitUint8(0x54);
1159 EmitOperand(dst, src);
1160}
1161
1162
Aart Bik68555e92017-02-13 14:28:45 -08001163void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001164 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1165 EmitUint8(0x66);
1166 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001167 EmitUint8(0xDB);
1168 EmitXmmRegisterOperand(dst, src);
1169}
1170
1171
Aart Bik21c580b2017-03-13 11:52:07 -07001172void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
1173 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1174 EmitUint8(0x66);
1175 EmitUint8(0x0F);
1176 EmitUint8(0x55);
1177 EmitXmmRegisterOperand(dst, src);
1178}
1179
1180
1181void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
1182 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1183 EmitUint8(0x0F);
1184 EmitUint8(0x55);
1185 EmitXmmRegisterOperand(dst, src);
1186}
1187
1188
1189void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
1190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1191 EmitUint8(0x66);
1192 EmitUint8(0x0F);
1193 EmitUint8(0xDF);
1194 EmitXmmRegisterOperand(dst, src);
1195}
1196
1197
Aart Bik68555e92017-02-13 14:28:45 -08001198void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1199 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1200 EmitUint8(0x66);
1201 EmitUint8(0x0F);
1202 EmitUint8(0x56);
1203 EmitXmmRegisterOperand(dst, src);
1204}
1205
1206
1207void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1208 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1209 EmitUint8(0x0F);
1210 EmitUint8(0x56);
1211 EmitXmmRegisterOperand(dst, src);
1212}
1213
1214
1215void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1216 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1217 EmitUint8(0x66);
1218 EmitUint8(0x0F);
1219 EmitUint8(0xEB);
1220 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001221}
1222
1223
Aart Bik67d3fd72017-03-31 15:11:53 -07001224void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
1225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1226 EmitUint8(0x66);
1227 EmitUint8(0x0F);
1228 EmitUint8(0xE0);
1229 EmitXmmRegisterOperand(dst, src);
1230}
1231
1232
1233void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
1234 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1235 EmitUint8(0x66);
1236 EmitUint8(0x0F);
1237 EmitUint8(0xE3);
1238 EmitXmmRegisterOperand(dst, src);
1239}
1240
1241
Aart Bik4b455332017-03-15 11:19:35 -07001242void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
1243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1244 EmitUint8(0x66);
1245 EmitUint8(0x0F);
1246 EmitUint8(0x74);
1247 EmitXmmRegisterOperand(dst, src);
1248}
1249
1250
1251void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
1252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1253 EmitUint8(0x66);
1254 EmitUint8(0x0F);
1255 EmitUint8(0x75);
1256 EmitXmmRegisterOperand(dst, src);
1257}
1258
1259
1260void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
1261 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262 EmitUint8(0x66);
1263 EmitUint8(0x0F);
1264 EmitUint8(0x76);
1265 EmitXmmRegisterOperand(dst, src);
1266}
1267
1268
1269void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
1270 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1271 EmitUint8(0x66);
1272 EmitUint8(0x0F);
1273 EmitUint8(0x38);
1274 EmitUint8(0x29);
1275 EmitXmmRegisterOperand(dst, src);
1276}
1277
1278
Aart Bik12e06ed2017-01-31 16:11:24 -08001279void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1280 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1281 EmitUint8(0x66);
1282 EmitUint8(0x0F);
1283 EmitUint8(0xC6);
1284 EmitXmmRegisterOperand(dst, src);
1285 EmitUint8(imm.value());
1286}
1287
1288
1289void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1290 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1291 EmitUint8(0x0F);
1292 EmitUint8(0xC6);
1293 EmitXmmRegisterOperand(dst, src);
1294 EmitUint8(imm.value());
1295}
1296
1297
Aart Bik68555e92017-02-13 14:28:45 -08001298void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1299 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1300 EmitUint8(0x66);
1301 EmitUint8(0x0F);
1302 EmitUint8(0x70);
1303 EmitXmmRegisterOperand(dst, src);
1304 EmitUint8(imm.value());
1305}
1306
1307
Aart Bike69d7a92017-02-17 11:48:23 -08001308void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1309 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1310 EmitUint8(0x66);
1311 EmitUint8(0x0F);
1312 EmitUint8(0x60);
1313 EmitXmmRegisterOperand(dst, src);
1314}
1315
1316
1317void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1318 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1319 EmitUint8(0x66);
1320 EmitUint8(0x0F);
1321 EmitUint8(0x61);
1322 EmitXmmRegisterOperand(dst, src);
1323}
1324
1325
1326void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1327 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1328 EmitUint8(0x66);
1329 EmitUint8(0x0F);
1330 EmitUint8(0x62);
1331 EmitXmmRegisterOperand(dst, src);
1332}
1333
1334
1335void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1336 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1337 EmitUint8(0x66);
1338 EmitUint8(0x0F);
1339 EmitUint8(0x6C);
1340 EmitXmmRegisterOperand(dst, src);
1341}
1342
1343
1344void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1345 DCHECK(shift_count.is_uint8());
1346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1347 EmitUint8(0x66);
1348 EmitUint8(0x0F);
1349 EmitUint8(0x71);
1350 EmitXmmRegisterOperand(6, reg);
1351 EmitUint8(shift_count.value());
1352}
1353
1354
1355void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1356 DCHECK(shift_count.is_uint8());
1357 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1358 EmitUint8(0x66);
1359 EmitUint8(0x0F);
1360 EmitUint8(0x72);
1361 EmitXmmRegisterOperand(6, reg);
1362 EmitUint8(shift_count.value());
1363}
1364
1365
1366void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1367 DCHECK(shift_count.is_uint8());
1368 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1369 EmitUint8(0x66);
1370 EmitUint8(0x0F);
1371 EmitUint8(0x73);
1372 EmitXmmRegisterOperand(6, reg);
1373 EmitUint8(shift_count.value());
1374}
1375
1376
1377void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1378 DCHECK(shift_count.is_uint8());
1379 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1380 EmitUint8(0x66);
1381 EmitUint8(0x0F);
1382 EmitUint8(0x71);
1383 EmitXmmRegisterOperand(4, reg);
1384 EmitUint8(shift_count.value());
1385}
1386
1387
1388void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1389 DCHECK(shift_count.is_uint8());
1390 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1391 EmitUint8(0x66);
1392 EmitUint8(0x0F);
1393 EmitUint8(0x72);
1394 EmitXmmRegisterOperand(4, reg);
1395 EmitUint8(shift_count.value());
1396}
1397
1398
1399void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1400 DCHECK(shift_count.is_uint8());
1401 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1402 EmitUint8(0x66);
1403 EmitUint8(0x0F);
1404 EmitUint8(0x71);
1405 EmitXmmRegisterOperand(2, reg);
1406 EmitUint8(shift_count.value());
1407}
1408
1409
1410void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1411 DCHECK(shift_count.is_uint8());
1412 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1413 EmitUint8(0x66);
1414 EmitUint8(0x0F);
1415 EmitUint8(0x72);
1416 EmitXmmRegisterOperand(2, reg);
1417 EmitUint8(shift_count.value());
1418}
1419
1420
1421void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1422 DCHECK(shift_count.is_uint8());
1423 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1424 EmitUint8(0x66);
1425 EmitUint8(0x0F);
1426 EmitUint8(0x73);
1427 EmitXmmRegisterOperand(2, reg);
1428 EmitUint8(shift_count.value());
1429}
1430
1431
1432void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1433 DCHECK(shift_count.is_uint8());
1434 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1435 EmitUint8(0x66);
1436 EmitUint8(0x0F);
1437 EmitUint8(0x73);
1438 EmitXmmRegisterOperand(3, reg);
1439 EmitUint8(shift_count.value());
1440}
1441
1442
Ian Rogers2c8f6532011-09-02 17:16:34 -07001443void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001444 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1445 EmitUint8(0xDD);
1446 EmitOperand(0, src);
1447}
1448
1449
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001450void X86Assembler::fstl(const Address& dst) {
1451 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1452 EmitUint8(0xDD);
1453 EmitOperand(2, dst);
1454}
1455
1456
Ian Rogers2c8f6532011-09-02 17:16:34 -07001457void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1459 EmitUint8(0xDD);
1460 EmitOperand(3, dst);
1461}
1462
1463
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001464void X86Assembler::fstsw() {
1465 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1466 EmitUint8(0x9B);
1467 EmitUint8(0xDF);
1468 EmitUint8(0xE0);
1469}
1470
1471
Ian Rogers2c8f6532011-09-02 17:16:34 -07001472void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001473 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1474 EmitUint8(0xD9);
1475 EmitOperand(7, dst);
1476}
1477
1478
Ian Rogers2c8f6532011-09-02 17:16:34 -07001479void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001480 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1481 EmitUint8(0xD9);
1482 EmitOperand(5, src);
1483}
1484
1485
Ian Rogers2c8f6532011-09-02 17:16:34 -07001486void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001487 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1488 EmitUint8(0xDF);
1489 EmitOperand(7, dst);
1490}
1491
1492
Ian Rogers2c8f6532011-09-02 17:16:34 -07001493void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1495 EmitUint8(0xDB);
1496 EmitOperand(3, dst);
1497}
1498
1499
Ian Rogers2c8f6532011-09-02 17:16:34 -07001500void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001501 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1502 EmitUint8(0xDF);
1503 EmitOperand(5, src);
1504}
1505
1506
Roland Levillain0a186012015-04-13 17:00:20 +01001507void X86Assembler::filds(const Address& src) {
1508 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1509 EmitUint8(0xDB);
1510 EmitOperand(0, src);
1511}
1512
1513
Ian Rogers2c8f6532011-09-02 17:16:34 -07001514void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001515 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1516 EmitUint8(0xD9);
1517 EmitUint8(0xF7);
1518}
1519
1520
Ian Rogers2c8f6532011-09-02 17:16:34 -07001521void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001522 CHECK_LT(index.value(), 7);
1523 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1524 EmitUint8(0xDD);
1525 EmitUint8(0xC0 + index.value());
1526}
1527
1528
Ian Rogers2c8f6532011-09-02 17:16:34 -07001529void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001530 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1531 EmitUint8(0xD9);
1532 EmitUint8(0xFE);
1533}
1534
1535
Ian Rogers2c8f6532011-09-02 17:16:34 -07001536void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001537 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1538 EmitUint8(0xD9);
1539 EmitUint8(0xFF);
1540}
1541
1542
Ian Rogers2c8f6532011-09-02 17:16:34 -07001543void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1545 EmitUint8(0xD9);
1546 EmitUint8(0xF2);
1547}
1548
1549
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001550void X86Assembler::fucompp() {
1551 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1552 EmitUint8(0xDA);
1553 EmitUint8(0xE9);
1554}
1555
1556
1557void X86Assembler::fprem() {
1558 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1559 EmitUint8(0xD9);
1560 EmitUint8(0xF8);
1561}
1562
1563
Ian Rogers2c8f6532011-09-02 17:16:34 -07001564void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001565 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1566 EmitUint8(0x87);
1567 EmitRegisterOperand(dst, src);
1568}
1569
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001570
Ian Rogers7caad772012-03-30 01:07:54 -07001571void X86Assembler::xchgl(Register reg, const Address& address) {
1572 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1573 EmitUint8(0x87);
1574 EmitOperand(reg, address);
1575}
1576
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001577
Serguei Katkov3b625932016-05-06 10:24:17 +06001578void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1579 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1580 EmitUint8(0x80);
1581 EmitOperand(7, address);
1582 EmitUint8(imm.value() & 0xFF);
1583}
1584
1585
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001586void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1588 EmitUint8(0x66);
1589 EmitComplex(7, address, imm);
1590}
1591
1592
Ian Rogers2c8f6532011-09-02 17:16:34 -07001593void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1595 EmitComplex(7, Operand(reg), imm);
1596}
1597
1598
Ian Rogers2c8f6532011-09-02 17:16:34 -07001599void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001600 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1601 EmitUint8(0x3B);
1602 EmitOperand(reg0, Operand(reg1));
1603}
1604
1605
Ian Rogers2c8f6532011-09-02 17:16:34 -07001606void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001607 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1608 EmitUint8(0x3B);
1609 EmitOperand(reg, address);
1610}
1611
1612
Ian Rogers2c8f6532011-09-02 17:16:34 -07001613void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001614 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1615 EmitUint8(0x03);
1616 EmitRegisterOperand(dst, src);
1617}
1618
1619
Ian Rogers2c8f6532011-09-02 17:16:34 -07001620void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001621 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1622 EmitUint8(0x03);
1623 EmitOperand(reg, address);
1624}
1625
1626
Ian Rogers2c8f6532011-09-02 17:16:34 -07001627void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1629 EmitUint8(0x39);
1630 EmitOperand(reg, address);
1631}
1632
1633
Ian Rogers2c8f6532011-09-02 17:16:34 -07001634void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001635 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1636 EmitComplex(7, address, imm);
1637}
1638
1639
Ian Rogers2c8f6532011-09-02 17:16:34 -07001640void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001641 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1642 EmitUint8(0x85);
1643 EmitRegisterOperand(reg1, reg2);
1644}
1645
1646
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001647void X86Assembler::testl(Register reg, const Address& address) {
1648 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1649 EmitUint8(0x85);
1650 EmitOperand(reg, address);
1651}
1652
1653
Ian Rogers2c8f6532011-09-02 17:16:34 -07001654void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1656 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1657 // we only test the byte register to keep the encoding short.
1658 if (immediate.is_uint8() && reg < 4) {
1659 // Use zero-extended 8-bit immediate.
1660 if (reg == EAX) {
1661 EmitUint8(0xA8);
1662 } else {
1663 EmitUint8(0xF6);
1664 EmitUint8(0xC0 + reg);
1665 }
1666 EmitUint8(immediate.value() & 0xFF);
1667 } else if (reg == EAX) {
1668 // Use short form if the destination is EAX.
1669 EmitUint8(0xA9);
1670 EmitImmediate(immediate);
1671 } else {
1672 EmitUint8(0xF7);
1673 EmitOperand(0, Operand(reg));
1674 EmitImmediate(immediate);
1675 }
1676}
1677
1678
Vladimir Marko953437b2016-08-24 08:30:46 +00001679void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1680 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1681 EmitUint8(0xF6);
1682 EmitOperand(EAX, dst);
1683 CHECK(imm.is_int8());
1684 EmitUint8(imm.value() & 0xFF);
1685}
1686
1687
1688void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1689 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1690 EmitUint8(0xF7);
1691 EmitOperand(0, dst);
1692 EmitImmediate(imm);
1693}
1694
1695
Ian Rogers2c8f6532011-09-02 17:16:34 -07001696void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001697 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1698 EmitUint8(0x23);
1699 EmitOperand(dst, Operand(src));
1700}
1701
1702
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001703void X86Assembler::andl(Register reg, const Address& address) {
1704 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1705 EmitUint8(0x23);
1706 EmitOperand(reg, address);
1707}
1708
1709
Ian Rogers2c8f6532011-09-02 17:16:34 -07001710void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001711 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1712 EmitComplex(4, Operand(dst), imm);
1713}
1714
1715
Ian Rogers2c8f6532011-09-02 17:16:34 -07001716void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001717 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1718 EmitUint8(0x0B);
1719 EmitOperand(dst, Operand(src));
1720}
1721
1722
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001723void X86Assembler::orl(Register reg, const Address& address) {
1724 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1725 EmitUint8(0x0B);
1726 EmitOperand(reg, address);
1727}
1728
1729
Ian Rogers2c8f6532011-09-02 17:16:34 -07001730void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001731 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1732 EmitComplex(1, Operand(dst), imm);
1733}
1734
1735
Ian Rogers2c8f6532011-09-02 17:16:34 -07001736void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001737 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1738 EmitUint8(0x33);
1739 EmitOperand(dst, Operand(src));
1740}
1741
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001742
1743void X86Assembler::xorl(Register reg, const Address& address) {
1744 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1745 EmitUint8(0x33);
1746 EmitOperand(reg, address);
1747}
1748
1749
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01001750void X86Assembler::xorl(Register dst, const Immediate& imm) {
1751 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1752 EmitComplex(6, Operand(dst), imm);
1753}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001754
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001755
Ian Rogers2c8f6532011-09-02 17:16:34 -07001756void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001757 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1758 EmitComplex(0, Operand(reg), imm);
1759}
1760
1761
Ian Rogers2c8f6532011-09-02 17:16:34 -07001762void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1764 EmitUint8(0x01);
1765 EmitOperand(reg, address);
1766}
1767
1768
Ian Rogers2c8f6532011-09-02 17:16:34 -07001769void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001770 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1771 EmitComplex(0, address, imm);
1772}
1773
1774
Ian Rogers2c8f6532011-09-02 17:16:34 -07001775void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001776 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1777 EmitComplex(2, Operand(reg), imm);
1778}
1779
1780
Ian Rogers2c8f6532011-09-02 17:16:34 -07001781void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001782 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1783 EmitUint8(0x13);
1784 EmitOperand(dst, Operand(src));
1785}
1786
1787
Ian Rogers2c8f6532011-09-02 17:16:34 -07001788void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001789 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1790 EmitUint8(0x13);
1791 EmitOperand(dst, address);
1792}
1793
1794
Ian Rogers2c8f6532011-09-02 17:16:34 -07001795void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001796 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1797 EmitUint8(0x2B);
1798 EmitOperand(dst, Operand(src));
1799}
1800
1801
Ian Rogers2c8f6532011-09-02 17:16:34 -07001802void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001803 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1804 EmitComplex(5, Operand(reg), imm);
1805}
1806
1807
Ian Rogers2c8f6532011-09-02 17:16:34 -07001808void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001809 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1810 EmitUint8(0x2B);
1811 EmitOperand(reg, address);
1812}
1813
1814
Mark Mendell09ed1a32015-03-25 08:30:06 -04001815void X86Assembler::subl(const Address& address, Register reg) {
1816 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1817 EmitUint8(0x29);
1818 EmitOperand(reg, address);
1819}
1820
1821
Ian Rogers2c8f6532011-09-02 17:16:34 -07001822void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001823 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1824 EmitUint8(0x99);
1825}
1826
1827
Ian Rogers2c8f6532011-09-02 17:16:34 -07001828void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001829 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1830 EmitUint8(0xF7);
1831 EmitUint8(0xF8 | reg);
1832}
1833
1834
Ian Rogers2c8f6532011-09-02 17:16:34 -07001835void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001836 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1837 EmitUint8(0x0F);
1838 EmitUint8(0xAF);
1839 EmitOperand(dst, Operand(src));
1840}
1841
1842
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001843void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001845 // See whether imm can be represented as a sign-extended 8bit value.
1846 int32_t v32 = static_cast<int32_t>(imm.value());
1847 if (IsInt<8>(v32)) {
1848 // Sign-extension works.
1849 EmitUint8(0x6B);
1850 EmitOperand(dst, Operand(src));
1851 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
1852 } else {
1853 // Not representable, use full immediate.
1854 EmitUint8(0x69);
1855 EmitOperand(dst, Operand(src));
1856 EmitImmediate(imm);
1857 }
1858}
1859
1860
1861void X86Assembler::imull(Register reg, const Immediate& imm) {
1862 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001863}
1864
1865
Ian Rogers2c8f6532011-09-02 17:16:34 -07001866void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001867 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1868 EmitUint8(0x0F);
1869 EmitUint8(0xAF);
1870 EmitOperand(reg, address);
1871}
1872
1873
Ian Rogers2c8f6532011-09-02 17:16:34 -07001874void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001875 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1876 EmitUint8(0xF7);
1877 EmitOperand(5, Operand(reg));
1878}
1879
1880
Ian Rogers2c8f6532011-09-02 17:16:34 -07001881void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001882 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1883 EmitUint8(0xF7);
1884 EmitOperand(5, address);
1885}
1886
1887
Ian Rogers2c8f6532011-09-02 17:16:34 -07001888void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001889 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1890 EmitUint8(0xF7);
1891 EmitOperand(4, Operand(reg));
1892}
1893
1894
Ian Rogers2c8f6532011-09-02 17:16:34 -07001895void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001896 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1897 EmitUint8(0xF7);
1898 EmitOperand(4, address);
1899}
1900
1901
Ian Rogers2c8f6532011-09-02 17:16:34 -07001902void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001903 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1904 EmitUint8(0x1B);
1905 EmitOperand(dst, Operand(src));
1906}
1907
1908
Ian Rogers2c8f6532011-09-02 17:16:34 -07001909void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001910 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1911 EmitComplex(3, Operand(reg), imm);
1912}
1913
1914
Ian Rogers2c8f6532011-09-02 17:16:34 -07001915void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001916 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1917 EmitUint8(0x1B);
1918 EmitOperand(dst, address);
1919}
1920
1921
Mark Mendell09ed1a32015-03-25 08:30:06 -04001922void X86Assembler::sbbl(const Address& address, Register src) {
1923 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1924 EmitUint8(0x19);
1925 EmitOperand(src, address);
1926}
1927
1928
Ian Rogers2c8f6532011-09-02 17:16:34 -07001929void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001930 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1931 EmitUint8(0x40 + reg);
1932}
1933
1934
Ian Rogers2c8f6532011-09-02 17:16:34 -07001935void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001936 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1937 EmitUint8(0xFF);
1938 EmitOperand(0, address);
1939}
1940
1941
Ian Rogers2c8f6532011-09-02 17:16:34 -07001942void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001943 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1944 EmitUint8(0x48 + reg);
1945}
1946
1947
Ian Rogers2c8f6532011-09-02 17:16:34 -07001948void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001949 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1950 EmitUint8(0xFF);
1951 EmitOperand(1, address);
1952}
1953
1954
Ian Rogers2c8f6532011-09-02 17:16:34 -07001955void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001956 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001957}
1958
1959
Ian Rogers2c8f6532011-09-02 17:16:34 -07001960void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001961 EmitGenericShift(4, Operand(operand), shifter);
1962}
1963
1964
1965void X86Assembler::shll(const Address& address, const Immediate& imm) {
1966 EmitGenericShift(4, address, imm);
1967}
1968
1969
1970void X86Assembler::shll(const Address& address, Register shifter) {
1971 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001972}
1973
1974
Ian Rogers2c8f6532011-09-02 17:16:34 -07001975void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001976 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001977}
1978
1979
Ian Rogers2c8f6532011-09-02 17:16:34 -07001980void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001981 EmitGenericShift(5, Operand(operand), shifter);
1982}
1983
1984
1985void X86Assembler::shrl(const Address& address, const Immediate& imm) {
1986 EmitGenericShift(5, address, imm);
1987}
1988
1989
1990void X86Assembler::shrl(const Address& address, Register shifter) {
1991 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001992}
1993
1994
Ian Rogers2c8f6532011-09-02 17:16:34 -07001995void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001996 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001997}
1998
1999
Ian Rogers2c8f6532011-09-02 17:16:34 -07002000void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002001 EmitGenericShift(7, Operand(operand), shifter);
2002}
2003
2004
2005void X86Assembler::sarl(const Address& address, const Immediate& imm) {
2006 EmitGenericShift(7, address, imm);
2007}
2008
2009
2010void X86Assembler::sarl(const Address& address, Register shifter) {
2011 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002012}
2013
2014
Calin Juravle9aec02f2014-11-18 23:06:35 +00002015void X86Assembler::shld(Register dst, Register src, Register shifter) {
2016 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002017 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2018 EmitUint8(0x0F);
2019 EmitUint8(0xA5);
2020 EmitRegisterOperand(src, dst);
2021}
2022
2023
Mark P Mendell73945692015-04-29 14:56:17 +00002024void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
2025 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2026 EmitUint8(0x0F);
2027 EmitUint8(0xA4);
2028 EmitRegisterOperand(src, dst);
2029 EmitUint8(imm.value() & 0xFF);
2030}
2031
2032
Calin Juravle9aec02f2014-11-18 23:06:35 +00002033void X86Assembler::shrd(Register dst, Register src, Register shifter) {
2034 DCHECK_EQ(ECX, shifter);
2035 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2036 EmitUint8(0x0F);
2037 EmitUint8(0xAD);
2038 EmitRegisterOperand(src, dst);
2039}
2040
2041
Mark P Mendell73945692015-04-29 14:56:17 +00002042void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
2043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2044 EmitUint8(0x0F);
2045 EmitUint8(0xAC);
2046 EmitRegisterOperand(src, dst);
2047 EmitUint8(imm.value() & 0xFF);
2048}
2049
2050
Mark Mendellbcee0922015-09-15 21:45:01 -04002051void X86Assembler::roll(Register reg, const Immediate& imm) {
2052 EmitGenericShift(0, Operand(reg), imm);
2053}
2054
2055
2056void X86Assembler::roll(Register operand, Register shifter) {
2057 EmitGenericShift(0, Operand(operand), shifter);
2058}
2059
2060
2061void X86Assembler::rorl(Register reg, const Immediate& imm) {
2062 EmitGenericShift(1, Operand(reg), imm);
2063}
2064
2065
2066void X86Assembler::rorl(Register operand, Register shifter) {
2067 EmitGenericShift(1, Operand(operand), shifter);
2068}
2069
2070
Ian Rogers2c8f6532011-09-02 17:16:34 -07002071void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002072 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2073 EmitUint8(0xF7);
2074 EmitOperand(3, Operand(reg));
2075}
2076
2077
Ian Rogers2c8f6532011-09-02 17:16:34 -07002078void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002079 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2080 EmitUint8(0xF7);
2081 EmitUint8(0xD0 | reg);
2082}
2083
2084
Ian Rogers2c8f6532011-09-02 17:16:34 -07002085void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002086 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2087 EmitUint8(0xC8);
2088 CHECK(imm.is_uint16());
2089 EmitUint8(imm.value() & 0xFF);
2090 EmitUint8((imm.value() >> 8) & 0xFF);
2091 EmitUint8(0x00);
2092}
2093
2094
Ian Rogers2c8f6532011-09-02 17:16:34 -07002095void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2097 EmitUint8(0xC9);
2098}
2099
2100
Ian Rogers2c8f6532011-09-02 17:16:34 -07002101void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002102 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2103 EmitUint8(0xC3);
2104}
2105
2106
Ian Rogers2c8f6532011-09-02 17:16:34 -07002107void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002108 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2109 EmitUint8(0xC2);
2110 CHECK(imm.is_uint16());
2111 EmitUint8(imm.value() & 0xFF);
2112 EmitUint8((imm.value() >> 8) & 0xFF);
2113}
2114
2115
2116
Ian Rogers2c8f6532011-09-02 17:16:34 -07002117void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002118 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2119 EmitUint8(0x90);
2120}
2121
2122
Ian Rogers2c8f6532011-09-02 17:16:34 -07002123void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002124 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2125 EmitUint8(0xCC);
2126}
2127
2128
Ian Rogers2c8f6532011-09-02 17:16:34 -07002129void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2131 EmitUint8(0xF4);
2132}
2133
2134
Ian Rogers2c8f6532011-09-02 17:16:34 -07002135void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002136 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2137 if (label->IsBound()) {
2138 static const int kShortSize = 2;
2139 static const int kLongSize = 6;
2140 int offset = label->Position() - buffer_.Size();
2141 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002142 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002143 EmitUint8(0x70 + condition);
2144 EmitUint8((offset - kShortSize) & 0xFF);
2145 } else {
2146 EmitUint8(0x0F);
2147 EmitUint8(0x80 + condition);
2148 EmitInt32(offset - kLongSize);
2149 }
2150 } else {
2151 EmitUint8(0x0F);
2152 EmitUint8(0x80 + condition);
2153 EmitLabelLink(label);
2154 }
2155}
2156
2157
Mark Mendell73f455e2015-08-21 09:30:05 -04002158void X86Assembler::j(Condition condition, NearLabel* label) {
2159 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2160 if (label->IsBound()) {
2161 static const int kShortSize = 2;
2162 int offset = label->Position() - buffer_.Size();
2163 CHECK_LE(offset, 0);
2164 CHECK(IsInt<8>(offset - kShortSize));
2165 EmitUint8(0x70 + condition);
2166 EmitUint8((offset - kShortSize) & 0xFF);
2167 } else {
2168 EmitUint8(0x70 + condition);
2169 EmitLabelLink(label);
2170 }
2171}
2172
2173
2174void X86Assembler::jecxz(NearLabel* label) {
2175 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2176 if (label->IsBound()) {
2177 static const int kShortSize = 2;
2178 int offset = label->Position() - buffer_.Size();
2179 CHECK_LE(offset, 0);
2180 CHECK(IsInt<8>(offset - kShortSize));
2181 EmitUint8(0xE3);
2182 EmitUint8((offset - kShortSize) & 0xFF);
2183 } else {
2184 EmitUint8(0xE3);
2185 EmitLabelLink(label);
2186 }
2187}
2188
2189
Ian Rogers2c8f6532011-09-02 17:16:34 -07002190void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002191 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2192 EmitUint8(0xFF);
2193 EmitRegisterOperand(4, reg);
2194}
2195
Ian Rogers7caad772012-03-30 01:07:54 -07002196void X86Assembler::jmp(const Address& address) {
2197 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2198 EmitUint8(0xFF);
2199 EmitOperand(4, address);
2200}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002201
Ian Rogers2c8f6532011-09-02 17:16:34 -07002202void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2204 if (label->IsBound()) {
2205 static const int kShortSize = 2;
2206 static const int kLongSize = 5;
2207 int offset = label->Position() - buffer_.Size();
2208 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002209 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002210 EmitUint8(0xEB);
2211 EmitUint8((offset - kShortSize) & 0xFF);
2212 } else {
2213 EmitUint8(0xE9);
2214 EmitInt32(offset - kLongSize);
2215 }
2216 } else {
2217 EmitUint8(0xE9);
2218 EmitLabelLink(label);
2219 }
2220}
2221
2222
Mark Mendell73f455e2015-08-21 09:30:05 -04002223void X86Assembler::jmp(NearLabel* label) {
2224 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2225 if (label->IsBound()) {
2226 static const int kShortSize = 2;
2227 int offset = label->Position() - buffer_.Size();
2228 CHECK_LE(offset, 0);
2229 CHECK(IsInt<8>(offset - kShortSize));
2230 EmitUint8(0xEB);
2231 EmitUint8((offset - kShortSize) & 0xFF);
2232 } else {
2233 EmitUint8(0xEB);
2234 EmitLabelLink(label);
2235 }
2236}
2237
2238
jessicahandojob03d6402016-09-07 12:16:53 -07002239void X86Assembler::repne_scasb() {
2240 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2241 EmitUint8(0xF2);
2242 EmitUint8(0xAE);
2243}
2244
2245
Andreas Gampe21030dd2015-05-07 14:46:15 -07002246void X86Assembler::repne_scasw() {
2247 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2248 EmitUint8(0x66);
2249 EmitUint8(0xF2);
2250 EmitUint8(0xAF);
2251}
2252
2253
jessicahandojob03d6402016-09-07 12:16:53 -07002254void X86Assembler::repe_cmpsb() {
2255 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2256 EmitUint8(0xF2);
2257 EmitUint8(0xA6);
2258}
2259
2260
agicsaki71311f82015-07-27 11:34:13 -07002261void X86Assembler::repe_cmpsw() {
2262 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2263 EmitUint8(0x66);
2264 EmitUint8(0xF3);
2265 EmitUint8(0xA7);
2266}
2267
2268
agicsaki970abfb2015-07-31 10:31:14 -07002269void X86Assembler::repe_cmpsl() {
2270 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2271 EmitUint8(0xF3);
2272 EmitUint8(0xA7);
2273}
2274
2275
jessicahandojob03d6402016-09-07 12:16:53 -07002276void X86Assembler::rep_movsb() {
2277 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2278 EmitUint8(0xF3);
2279 EmitUint8(0xA4);
2280}
2281
2282
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002283void X86Assembler::rep_movsw() {
2284 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2285 EmitUint8(0x66);
2286 EmitUint8(0xF3);
2287 EmitUint8(0xA5);
2288}
2289
2290
Ian Rogers2c8f6532011-09-02 17:16:34 -07002291X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002292 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2293 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002294 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002295}
2296
2297
Ian Rogers2c8f6532011-09-02 17:16:34 -07002298void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002299 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2300 EmitUint8(0x0F);
2301 EmitUint8(0xB1);
2302 EmitOperand(reg, address);
2303}
2304
Mark Mendell58d25fd2015-04-03 14:52:31 -04002305
2306void X86Assembler::cmpxchg8b(const Address& address) {
2307 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2308 EmitUint8(0x0F);
2309 EmitUint8(0xC7);
2310 EmitOperand(1, address);
2311}
2312
2313
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002314void X86Assembler::mfence() {
2315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2316 EmitUint8(0x0F);
2317 EmitUint8(0xAE);
2318 EmitUint8(0xF0);
2319}
2320
Ian Rogers2c8f6532011-09-02 17:16:34 -07002321X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002322 // TODO: fs is a prefix and not an instruction
2323 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2324 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002325 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002326}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002327
Ian Rogersbefbd572014-03-06 01:13:39 -08002328X86Assembler* X86Assembler::gs() {
2329 // TODO: fs is a prefix and not an instruction
2330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2331 EmitUint8(0x65);
2332 return this;
2333}
2334
Ian Rogers2c8f6532011-09-02 17:16:34 -07002335void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002336 int value = imm.value();
2337 if (value > 0) {
2338 if (value == 1) {
2339 incl(reg);
2340 } else if (value != 0) {
2341 addl(reg, imm);
2342 }
2343 } else if (value < 0) {
2344 value = -value;
2345 if (value == 1) {
2346 decl(reg);
2347 } else if (value != 0) {
2348 subl(reg, Immediate(value));
2349 }
2350 }
2351}
2352
2353
Roland Levillain647b9ed2014-11-27 12:06:00 +00002354void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2355 // TODO: Need to have a code constants table.
2356 pushl(Immediate(High32Bits(value)));
2357 pushl(Immediate(Low32Bits(value)));
2358 movsd(dst, Address(ESP, 0));
2359 addl(ESP, Immediate(2 * sizeof(int32_t)));
2360}
2361
2362
Ian Rogers2c8f6532011-09-02 17:16:34 -07002363void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002364 // TODO: Need to have a code constants table.
2365 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002366 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002367}
2368
2369
Ian Rogers2c8f6532011-09-02 17:16:34 -07002370void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002371 CHECK(IsPowerOfTwo(alignment));
2372 // Emit nop instruction until the real position is aligned.
2373 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2374 nop();
2375 }
2376}
2377
2378
Ian Rogers2c8f6532011-09-02 17:16:34 -07002379void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002380 int bound = buffer_.Size();
2381 CHECK(!label->IsBound()); // Labels can only be bound once.
2382 while (label->IsLinked()) {
2383 int position = label->LinkPosition();
2384 int next = buffer_.Load<int32_t>(position);
2385 buffer_.Store<int32_t>(position, bound - (position + 4));
2386 label->position_ = next;
2387 }
2388 label->BindTo(bound);
2389}
2390
2391
Mark Mendell73f455e2015-08-21 09:30:05 -04002392void X86Assembler::Bind(NearLabel* label) {
2393 int bound = buffer_.Size();
2394 CHECK(!label->IsBound()); // Labels can only be bound once.
2395 while (label->IsLinked()) {
2396 int position = label->LinkPosition();
2397 uint8_t delta = buffer_.Load<uint8_t>(position);
2398 int offset = bound - (position + 1);
2399 CHECK(IsInt<8>(offset));
2400 buffer_.Store<int8_t>(position, offset);
2401 label->position_ = delta != 0u ? label->position_ - delta : 0;
2402 }
2403 label->BindTo(bound);
2404}
2405
2406
Ian Rogers44fb0d02012-03-23 16:46:24 -07002407void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2408 CHECK_GE(reg_or_opcode, 0);
2409 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002410 const int length = operand.length_;
2411 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002412 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002413 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002414 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002415 // Emit the rest of the encoded operand.
2416 for (int i = 1; i < length; i++) {
2417 EmitUint8(operand.encoding_[i]);
2418 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002419 AssemblerFixup* fixup = operand.GetFixup();
2420 if (fixup != nullptr) {
2421 EmitFixup(fixup);
2422 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002423}
2424
2425
Ian Rogers2c8f6532011-09-02 17:16:34 -07002426void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002427 EmitInt32(imm.value());
2428}
2429
2430
Ian Rogers44fb0d02012-03-23 16:46:24 -07002431void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002432 const Operand& operand,
2433 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002434 CHECK_GE(reg_or_opcode, 0);
2435 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002436 if (immediate.is_int8()) {
2437 // Use sign-extended 8-bit immediate.
2438 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002439 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002440 EmitUint8(immediate.value() & 0xFF);
2441 } else if (operand.IsRegister(EAX)) {
2442 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002443 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002444 EmitImmediate(immediate);
2445 } else {
2446 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002447 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002448 EmitImmediate(immediate);
2449 }
2450}
2451
2452
Ian Rogers2c8f6532011-09-02 17:16:34 -07002453void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002454 if (label->IsBound()) {
2455 int offset = label->Position() - buffer_.Size();
2456 CHECK_LE(offset, 0);
2457 EmitInt32(offset - instruction_size);
2458 } else {
2459 EmitLabelLink(label);
2460 }
2461}
2462
2463
Ian Rogers2c8f6532011-09-02 17:16:34 -07002464void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002465 CHECK(!label->IsBound());
2466 int position = buffer_.Size();
2467 EmitInt32(label->position_);
2468 label->LinkTo(position);
2469}
2470
2471
Mark Mendell73f455e2015-08-21 09:30:05 -04002472void X86Assembler::EmitLabelLink(NearLabel* label) {
2473 CHECK(!label->IsBound());
2474 int position = buffer_.Size();
2475 if (label->IsLinked()) {
2476 // Save the delta in the byte that we have to play with.
2477 uint32_t delta = position - label->LinkPosition();
2478 CHECK(IsUint<8>(delta));
2479 EmitUint8(delta & 0xFF);
2480 } else {
2481 EmitUint8(0);
2482 }
2483 label->LinkTo(position);
2484}
2485
2486
Ian Rogers44fb0d02012-03-23 16:46:24 -07002487void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002488 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002489 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002490 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2491 CHECK(imm.is_int8());
2492 if (imm.value() == 1) {
2493 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002494 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002495 } else {
2496 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002497 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002498 EmitUint8(imm.value() & 0xFF);
2499 }
2500}
2501
2502
Ian Rogers44fb0d02012-03-23 16:46:24 -07002503void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002504 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002505 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002506 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2507 CHECK_EQ(shifter, ECX);
2508 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002509 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002510}
2511
Mark Mendell0616ae02015-04-17 12:49:27 -04002512void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002513 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002514 // Generate the data for the literal area.
2515 for (size_t i = 0, e = area.size(); i < e; i++) {
2516 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2517 EmitInt32(area[i]);
2518 }
2519}
2520
Mark Mendell805b3b52015-09-18 14:10:29 -04002521size_t ConstantArea::AppendInt32(int32_t v) {
2522 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002523 buffer_.push_back(v);
2524 return result;
2525}
2526
Mark Mendell805b3b52015-09-18 14:10:29 -04002527size_t ConstantArea::AddInt32(int32_t v) {
2528 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2529 if (v == buffer_[i]) {
2530 return i * elem_size_;
2531 }
2532 }
2533
2534 // Didn't match anything.
2535 return AppendInt32(v);
2536}
2537
2538size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002539 int32_t v_low = Low32Bits(v);
2540 int32_t v_high = High32Bits(v);
2541 if (buffer_.size() > 1) {
2542 // Ensure we don't pass the end of the buffer.
2543 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2544 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002545 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002546 }
2547 }
2548 }
2549
2550 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002551 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002552 buffer_.push_back(v_low);
2553 buffer_.push_back(v_high);
2554 return result;
2555}
2556
Mark Mendell805b3b52015-09-18 14:10:29 -04002557size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002558 // Treat the value as a 64-bit integer value.
2559 return AddInt64(bit_cast<int64_t, double>(v));
2560}
2561
Mark Mendell805b3b52015-09-18 14:10:29 -04002562size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002563 // Treat the value as a 32-bit integer value.
2564 return AddInt32(bit_cast<int32_t, float>(v));
2565}
2566
Ian Rogers2c8f6532011-09-02 17:16:34 -07002567} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002568} // namespace art