blob: ea160c8993cc31acfded51bcbd39e7a60877674e [file] [log] [blame]
Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Aart Bikcaa31e72017-09-14 17:08:50 -070035std::ostream& operator<<(std::ostream& os, const Address& addr) {
36 switch (addr.mod()) {
37 case 0:
Aart Bikf7754e82017-09-20 10:33:06 -070038 if (addr.rm() != ESP || addr.index() == ESP) {
39 return os << "(%" << addr.rm() << ")";
40 } else if (addr.base() == EBP) {
41 return os << static_cast<int>(addr.disp32()) << "(,%" << addr.index()
42 << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070043 }
Aart Bikf7754e82017-09-20 10:33:06 -070044 return os << "(%" << addr.base() << ",%" << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070045 case 1:
Aart Bikf7754e82017-09-20 10:33:06 -070046 if (addr.rm() != ESP || addr.index() == ESP) {
47 return os << static_cast<int>(addr.disp8()) << "(%" << addr.rm() << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070048 }
Aart Bikf7754e82017-09-20 10:33:06 -070049 return os << static_cast<int>(addr.disp8()) << "(%" << addr.base() << ",%"
50 << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070051 case 2:
Aart Bikf7754e82017-09-20 10:33:06 -070052 if (addr.rm() != ESP || addr.index() == ESP) {
53 return os << static_cast<int>(addr.disp32()) << "(%" << addr.rm() << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070054 }
Aart Bikf7754e82017-09-20 10:33:06 -070055 return os << static_cast<int>(addr.disp32()) << "(%" << addr.base() << ",%"
56 << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070057 default:
58 return os << "<address?>";
59 }
60}
61
Ian Rogers2c8f6532011-09-02 17:16:34 -070062void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070063 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
64 EmitUint8(0xFF);
65 EmitRegisterOperand(2, reg);
66}
67
68
Ian Rogers2c8f6532011-09-02 17:16:34 -070069void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070070 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71 EmitUint8(0xFF);
72 EmitOperand(2, address);
73}
74
75
Ian Rogers2c8f6532011-09-02 17:16:34 -070076void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070077 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
78 EmitUint8(0xE8);
79 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000080 // Offset by one because we already have emitted the opcode.
81 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082}
83
84
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000085void X86Assembler::call(const ExternalLabel& label) {
86 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
87 intptr_t call_start = buffer_.GetPosition();
88 EmitUint8(0xE8);
89 EmitInt32(label.address());
90 static const intptr_t kCallExternalLabelSize = 5;
91 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
92}
93
94
Ian Rogers2c8f6532011-09-02 17:16:34 -070095void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
97 EmitUint8(0x50 + reg);
98}
99
100
Ian Rogers2c8f6532011-09-02 17:16:34 -0700101void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700102 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
103 EmitUint8(0xFF);
104 EmitOperand(6, address);
105}
106
107
Ian Rogers2c8f6532011-09-02 17:16:34 -0700108void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700109 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -0700110 if (imm.is_int8()) {
111 EmitUint8(0x6A);
112 EmitUint8(imm.value() & 0xFF);
113 } else {
114 EmitUint8(0x68);
115 EmitImmediate(imm);
116 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x58 + reg);
123}
124
125
Ian Rogers2c8f6532011-09-02 17:16:34 -0700126void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700127 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
128 EmitUint8(0x8F);
129 EmitOperand(0, address);
130}
131
132
Ian Rogers2c8f6532011-09-02 17:16:34 -0700133void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700134 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
135 EmitUint8(0xB8 + dst);
136 EmitImmediate(imm);
137}
138
139
Ian Rogers2c8f6532011-09-02 17:16:34 -0700140void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700141 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
142 EmitUint8(0x89);
143 EmitRegisterOperand(src, dst);
144}
145
146
Ian Rogers2c8f6532011-09-02 17:16:34 -0700147void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
149 EmitUint8(0x8B);
150 EmitOperand(dst, src);
151}
152
153
Ian Rogers2c8f6532011-09-02 17:16:34 -0700154void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700155 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
156 EmitUint8(0x89);
157 EmitOperand(src, dst);
158}
159
160
Ian Rogers2c8f6532011-09-02 17:16:34 -0700161void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0xC7);
164 EmitOperand(0, dst);
165 EmitImmediate(imm);
166}
167
Ian Rogersbdb03912011-09-14 00:55:44 -0700168void X86Assembler::movl(const Address& dst, Label* lbl) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0xC7);
171 EmitOperand(0, dst);
172 EmitLabel(lbl, dst.length_ + 5);
173}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700174
Mark Mendell7a08fb52015-07-15 14:09:35 -0400175void X86Assembler::movntl(const Address& dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xC3);
179 EmitOperand(src, dst);
180}
181
Mark Mendell09ed1a32015-03-25 08:30:06 -0400182void X86Assembler::bswapl(Register dst) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xC8 + dst);
186}
187
Mark Mendellbcee0922015-09-15 21:45:01 -0400188void X86Assembler::bsfl(Register dst, Register src) {
189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
190 EmitUint8(0x0F);
191 EmitUint8(0xBC);
192 EmitRegisterOperand(dst, src);
193}
194
195void X86Assembler::bsfl(Register dst, const Address& src) {
196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
197 EmitUint8(0x0F);
198 EmitUint8(0xBC);
199 EmitOperand(dst, src);
200}
201
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400202void X86Assembler::bsrl(Register dst, Register src) {
203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
204 EmitUint8(0x0F);
205 EmitUint8(0xBD);
206 EmitRegisterOperand(dst, src);
207}
208
209void X86Assembler::bsrl(Register dst, const Address& src) {
210 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
211 EmitUint8(0x0F);
212 EmitUint8(0xBD);
213 EmitOperand(dst, src);
214}
215
Aart Bikc39dac12016-01-21 08:59:48 -0800216void X86Assembler::popcntl(Register dst, Register src) {
217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
218 EmitUint8(0xF3);
219 EmitUint8(0x0F);
220 EmitUint8(0xB8);
221 EmitRegisterOperand(dst, src);
222}
223
224void X86Assembler::popcntl(Register dst, const Address& src) {
225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
226 EmitUint8(0xF3);
227 EmitUint8(0x0F);
228 EmitUint8(0xB8);
229 EmitOperand(dst, src);
230}
231
Ian Rogers2c8f6532011-09-02 17:16:34 -0700232void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700233 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
234 EmitUint8(0x0F);
235 EmitUint8(0xB6);
236 EmitRegisterOperand(dst, src);
237}
238
239
Ian Rogers2c8f6532011-09-02 17:16:34 -0700240void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700241 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
242 EmitUint8(0x0F);
243 EmitUint8(0xB6);
244 EmitOperand(dst, src);
245}
246
247
Ian Rogers2c8f6532011-09-02 17:16:34 -0700248void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700249 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
250 EmitUint8(0x0F);
251 EmitUint8(0xBE);
252 EmitRegisterOperand(dst, src);
253}
254
255
Ian Rogers2c8f6532011-09-02 17:16:34 -0700256void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700257 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
258 EmitUint8(0x0F);
259 EmitUint8(0xBE);
260 EmitOperand(dst, src);
261}
262
263
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700264void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700265 LOG(FATAL) << "Use movzxb or movsxb instead.";
266}
267
268
Ian Rogers2c8f6532011-09-02 17:16:34 -0700269void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700270 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
271 EmitUint8(0x88);
272 EmitOperand(src, dst);
273}
274
275
Ian Rogers2c8f6532011-09-02 17:16:34 -0700276void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700277 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
278 EmitUint8(0xC6);
279 EmitOperand(EAX, dst);
280 CHECK(imm.is_int8());
281 EmitUint8(imm.value() & 0xFF);
282}
283
284
Ian Rogers2c8f6532011-09-02 17:16:34 -0700285void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700286 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
287 EmitUint8(0x0F);
288 EmitUint8(0xB7);
289 EmitRegisterOperand(dst, src);
290}
291
292
Ian Rogers2c8f6532011-09-02 17:16:34 -0700293void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700294 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
295 EmitUint8(0x0F);
296 EmitUint8(0xB7);
297 EmitOperand(dst, src);
298}
299
300
Ian Rogers2c8f6532011-09-02 17:16:34 -0700301void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700302 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
303 EmitUint8(0x0F);
304 EmitUint8(0xBF);
305 EmitRegisterOperand(dst, src);
306}
307
308
Ian Rogers2c8f6532011-09-02 17:16:34 -0700309void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700310 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
311 EmitUint8(0x0F);
312 EmitUint8(0xBF);
313 EmitOperand(dst, src);
314}
315
316
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700317void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700318 LOG(FATAL) << "Use movzxw or movsxw instead.";
319}
320
321
Ian Rogers2c8f6532011-09-02 17:16:34 -0700322void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700323 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
324 EmitOperandSizeOverride();
325 EmitUint8(0x89);
326 EmitOperand(src, dst);
327}
328
329
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100330void X86Assembler::movw(const Address& dst, const Immediate& imm) {
331 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
332 EmitOperandSizeOverride();
333 EmitUint8(0xC7);
334 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100335 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100336 EmitUint8(imm.value() & 0xFF);
337 EmitUint8(imm.value() >> 8);
338}
339
340
Ian Rogers2c8f6532011-09-02 17:16:34 -0700341void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
343 EmitUint8(0x8D);
344 EmitOperand(dst, src);
345}
346
347
Ian Rogers2c8f6532011-09-02 17:16:34 -0700348void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700349 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
350 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700351 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700352 EmitRegisterOperand(dst, src);
353}
354
355
Mark Mendellabdac472016-02-12 13:49:03 -0500356void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
357 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
358 EmitUint8(0x0F);
359 EmitUint8(0x40 + condition);
360 EmitOperand(dst, src);
361}
362
363
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000364void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700365 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
366 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700367 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000368 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700369}
370
371
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100372void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
373 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
374 EmitUint8(0x0F);
375 EmitUint8(0x28);
376 EmitXmmRegisterOperand(dst, src);
377}
378
379
Aart Bikc7782262017-01-13 16:20:08 -0800380void X86Assembler::movaps(XmmRegister dst, const Address& src) {
381 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
382 EmitUint8(0x0F);
383 EmitUint8(0x28);
384 EmitOperand(dst, src);
385}
386
387
388void X86Assembler::movups(XmmRegister dst, const Address& src) {
389 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
390 EmitUint8(0x0F);
391 EmitUint8(0x10);
392 EmitOperand(dst, src);
393}
394
395
396void X86Assembler::movaps(const Address& dst, XmmRegister src) {
397 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
398 EmitUint8(0x0F);
399 EmitUint8(0x29);
400 EmitOperand(src, dst);
401}
402
403
404void X86Assembler::movups(const Address& dst, XmmRegister src) {
405 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0xF3);
415 EmitUint8(0x0F);
416 EmitUint8(0x10);
417 EmitOperand(dst, src);
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0xF3);
424 EmitUint8(0x0F);
425 EmitUint8(0x11);
426 EmitOperand(src, dst);
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x11);
435 EmitXmmRegisterOperand(src, dst);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0x66);
442 EmitUint8(0x0F);
443 EmitUint8(0x6E);
444 EmitOperand(dst, Operand(src));
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0x66);
451 EmitUint8(0x0F);
452 EmitUint8(0x7E);
453 EmitOperand(src, Operand(dst));
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x58);
462 EmitXmmRegisterOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x58);
471 EmitOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x5C);
480 EmitXmmRegisterOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5C);
489 EmitOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x59);
498 EmitXmmRegisterOperand(dst, src);
499}
500
501
Ian Rogers2c8f6532011-09-02 17:16:34 -0700502void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0xF3);
505 EmitUint8(0x0F);
506 EmitUint8(0x59);
507 EmitOperand(dst, src);
508}
509
510
Ian Rogers2c8f6532011-09-02 17:16:34 -0700511void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700512 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
513 EmitUint8(0xF3);
514 EmitUint8(0x0F);
515 EmitUint8(0x5E);
516 EmitXmmRegisterOperand(dst, src);
517}
518
519
Ian Rogers2c8f6532011-09-02 17:16:34 -0700520void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700521 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
522 EmitUint8(0xF3);
523 EmitUint8(0x0F);
524 EmitUint8(0x5E);
525 EmitOperand(dst, src);
526}
527
528
Aart Bikc7782262017-01-13 16:20:08 -0800529void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
530 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
531 EmitUint8(0x0F);
532 EmitUint8(0x58);
533 EmitXmmRegisterOperand(dst, src);
534}
535
536
537void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
538 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
539 EmitUint8(0x0F);
540 EmitUint8(0x5C);
541 EmitXmmRegisterOperand(dst, src);
542}
543
544
545void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
546 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
547 EmitUint8(0x0F);
548 EmitUint8(0x59);
549 EmitXmmRegisterOperand(dst, src);
550}
551
552
553void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
554 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
555 EmitUint8(0x0F);
556 EmitUint8(0x5E);
557 EmitXmmRegisterOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x28);
566 EmitXmmRegisterOperand(dst, src);
567}
568
569
570void X86Assembler::movapd(XmmRegister dst, const Address& src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x28);
575 EmitOperand(dst, src);
576}
577
578
579void X86Assembler::movupd(XmmRegister dst, const Address& src) {
580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0x66);
582 EmitUint8(0x0F);
583 EmitUint8(0x10);
584 EmitOperand(dst, src);
585}
586
587
588void X86Assembler::movapd(const Address& dst, XmmRegister src) {
589 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
590 EmitUint8(0x66);
591 EmitUint8(0x0F);
592 EmitUint8(0x29);
593 EmitOperand(src, dst);
594}
595
596
597void X86Assembler::movupd(const Address& dst, XmmRegister src) {
598 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
599 EmitUint8(0x66);
600 EmitUint8(0x0F);
601 EmitUint8(0x11);
602 EmitOperand(src, dst);
603}
604
605
Ian Rogers2c8f6532011-09-02 17:16:34 -0700606void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700607 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
608 EmitUint8(0xD9);
609 EmitOperand(0, src);
610}
611
612
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500613void X86Assembler::fsts(const Address& dst) {
614 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
615 EmitUint8(0xD9);
616 EmitOperand(2, dst);
617}
618
619
Ian Rogers2c8f6532011-09-02 17:16:34 -0700620void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700621 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
622 EmitUint8(0xD9);
623 EmitOperand(3, dst);
624}
625
626
Ian Rogers2c8f6532011-09-02 17:16:34 -0700627void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0xF2);
630 EmitUint8(0x0F);
631 EmitUint8(0x10);
632 EmitOperand(dst, src);
633}
634
635
Ian Rogers2c8f6532011-09-02 17:16:34 -0700636void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0xF2);
639 EmitUint8(0x0F);
640 EmitUint8(0x11);
641 EmitOperand(src, dst);
642}
643
644
Ian Rogers2c8f6532011-09-02 17:16:34 -0700645void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF2);
648 EmitUint8(0x0F);
649 EmitUint8(0x11);
650 EmitXmmRegisterOperand(src, dst);
651}
652
653
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000654void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0x66);
657 EmitUint8(0x0F);
658 EmitUint8(0x16);
659 EmitOperand(dst, src);
660}
661
662
663void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0x66);
666 EmitUint8(0x0F);
667 EmitUint8(0x17);
668 EmitOperand(src, dst);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF2);
675 EmitUint8(0x0F);
676 EmitUint8(0x58);
677 EmitXmmRegisterOperand(dst, src);
678}
679
680
Ian Rogers2c8f6532011-09-02 17:16:34 -0700681void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF2);
684 EmitUint8(0x0F);
685 EmitUint8(0x58);
686 EmitOperand(dst, src);
687}
688
689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF2);
693 EmitUint8(0x0F);
694 EmitUint8(0x5C);
695 EmitXmmRegisterOperand(dst, src);
696}
697
698
Ian Rogers2c8f6532011-09-02 17:16:34 -0700699void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0xF2);
702 EmitUint8(0x0F);
703 EmitUint8(0x5C);
704 EmitOperand(dst, src);
705}
706
707
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
710 EmitUint8(0xF2);
711 EmitUint8(0x0F);
712 EmitUint8(0x59);
713 EmitXmmRegisterOperand(dst, src);
714}
715
716
Ian Rogers2c8f6532011-09-02 17:16:34 -0700717void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
719 EmitUint8(0xF2);
720 EmitUint8(0x0F);
721 EmitUint8(0x59);
722 EmitOperand(dst, src);
723}
724
725
Ian Rogers2c8f6532011-09-02 17:16:34 -0700726void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
728 EmitUint8(0xF2);
729 EmitUint8(0x0F);
730 EmitUint8(0x5E);
731 EmitXmmRegisterOperand(dst, src);
732}
733
734
Ian Rogers2c8f6532011-09-02 17:16:34 -0700735void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
737 EmitUint8(0xF2);
738 EmitUint8(0x0F);
739 EmitUint8(0x5E);
740 EmitOperand(dst, src);
741}
742
743
Aart Bikc7782262017-01-13 16:20:08 -0800744void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
746 EmitUint8(0x66);
747 EmitUint8(0x0F);
748 EmitUint8(0x58);
749 EmitXmmRegisterOperand(dst, src);
750}
751
752
753void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755 EmitUint8(0x66);
756 EmitUint8(0x0F);
757 EmitUint8(0x5C);
758 EmitXmmRegisterOperand(dst, src);
759}
760
761
762void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
764 EmitUint8(0x66);
765 EmitUint8(0x0F);
766 EmitUint8(0x59);
767 EmitXmmRegisterOperand(dst, src);
768}
769
770
771void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
773 EmitUint8(0x66);
774 EmitUint8(0x0F);
775 EmitUint8(0x5E);
776 EmitXmmRegisterOperand(dst, src);
777}
778
779
Aart Bik68555e92017-02-13 14:28:45 -0800780void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
782 EmitUint8(0x66);
783 EmitUint8(0x0F);
784 EmitUint8(0x6F);
785 EmitXmmRegisterOperand(dst, src);
786}
787
788
789void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791 EmitUint8(0x66);
792 EmitUint8(0x0F);
793 EmitUint8(0x6F);
794 EmitOperand(dst, src);
795}
796
797
798void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
799 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
800 EmitUint8(0xF3);
801 EmitUint8(0x0F);
802 EmitUint8(0x6F);
803 EmitOperand(dst, src);
804}
805
806
807void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
809 EmitUint8(0x66);
810 EmitUint8(0x0F);
811 EmitUint8(0x7F);
812 EmitOperand(src, dst);
813}
814
815
816void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
818 EmitUint8(0xF3);
819 EmitUint8(0x0F);
820 EmitUint8(0x7F);
821 EmitOperand(src, dst);
822}
823
824
Aart Bike69d7a92017-02-17 11:48:23 -0800825void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
826 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827 EmitUint8(0x66);
828 EmitUint8(0x0F);
829 EmitUint8(0xFC);
830 EmitXmmRegisterOperand(dst, src);
831}
832
833
834void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836 EmitUint8(0x66);
837 EmitUint8(0x0F);
838 EmitUint8(0xF8);
839 EmitXmmRegisterOperand(dst, src);
840}
841
842
843void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
845 EmitUint8(0x66);
846 EmitUint8(0x0F);
847 EmitUint8(0xFD);
848 EmitXmmRegisterOperand(dst, src);
849}
850
851
852void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
854 EmitUint8(0x66);
855 EmitUint8(0x0F);
856 EmitUint8(0xF9);
857 EmitXmmRegisterOperand(dst, src);
858}
859
860
861void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0xD5);
866 EmitXmmRegisterOperand(dst, src);
867}
868
869
Aart Bik68555e92017-02-13 14:28:45 -0800870void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
871 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
872 EmitUint8(0x66);
873 EmitUint8(0x0F);
874 EmitUint8(0xFE);
875 EmitXmmRegisterOperand(dst, src);
876}
877
878
879void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
880 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
881 EmitUint8(0x66);
882 EmitUint8(0x0F);
883 EmitUint8(0xFA);
884 EmitXmmRegisterOperand(dst, src);
885}
886
887
888void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
889 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
890 EmitUint8(0x66);
891 EmitUint8(0x0F);
892 EmitUint8(0x38);
893 EmitUint8(0x40);
894 EmitXmmRegisterOperand(dst, src);
895}
896
897
Aart Bike69d7a92017-02-17 11:48:23 -0800898void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0x66);
901 EmitUint8(0x0F);
902 EmitUint8(0xD4);
903 EmitXmmRegisterOperand(dst, src);
904}
905
906
907void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
909 EmitUint8(0x66);
910 EmitUint8(0x0F);
911 EmitUint8(0xFB);
912 EmitXmmRegisterOperand(dst, src);
913}
914
915
Ian Rogers2c8f6532011-09-02 17:16:34 -0700916void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
918 EmitUint8(0xF3);
919 EmitUint8(0x0F);
920 EmitUint8(0x2A);
921 EmitOperand(dst, Operand(src));
922}
923
924
Ian Rogers2c8f6532011-09-02 17:16:34 -0700925void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700926 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
927 EmitUint8(0xF2);
928 EmitUint8(0x0F);
929 EmitUint8(0x2A);
930 EmitOperand(dst, Operand(src));
931}
932
933
Ian Rogers2c8f6532011-09-02 17:16:34 -0700934void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936 EmitUint8(0xF3);
937 EmitUint8(0x0F);
938 EmitUint8(0x2D);
939 EmitXmmRegisterOperand(dst, src);
940}
941
942
Ian Rogers2c8f6532011-09-02 17:16:34 -0700943void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
945 EmitUint8(0xF3);
946 EmitUint8(0x0F);
947 EmitUint8(0x5A);
948 EmitXmmRegisterOperand(dst, src);
949}
950
951
Ian Rogers2c8f6532011-09-02 17:16:34 -0700952void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954 EmitUint8(0xF2);
955 EmitUint8(0x0F);
956 EmitUint8(0x2D);
957 EmitXmmRegisterOperand(dst, src);
958}
959
960
Ian Rogers2c8f6532011-09-02 17:16:34 -0700961void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0xF3);
964 EmitUint8(0x0F);
965 EmitUint8(0x2C);
966 EmitXmmRegisterOperand(dst, src);
967}
968
969
Ian Rogers2c8f6532011-09-02 17:16:34 -0700970void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700971 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
972 EmitUint8(0xF2);
973 EmitUint8(0x0F);
974 EmitUint8(0x2C);
975 EmitXmmRegisterOperand(dst, src);
976}
977
978
Ian Rogers2c8f6532011-09-02 17:16:34 -0700979void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700980 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
981 EmitUint8(0xF2);
982 EmitUint8(0x0F);
983 EmitUint8(0x5A);
984 EmitXmmRegisterOperand(dst, src);
985}
986
987
Aart Bik3ae3b592017-02-24 14:09:15 -0800988void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
989 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
990 EmitUint8(0x0F);
991 EmitUint8(0x5B);
992 EmitXmmRegisterOperand(dst, src);
993}
994
995
Ian Rogers2c8f6532011-09-02 17:16:34 -0700996void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700997 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
998 EmitUint8(0xF3);
999 EmitUint8(0x0F);
1000 EmitUint8(0xE6);
1001 EmitXmmRegisterOperand(dst, src);
1002}
1003
1004
Ian Rogers2c8f6532011-09-02 17:16:34 -07001005void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001006 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1007 EmitUint8(0x0F);
1008 EmitUint8(0x2F);
1009 EmitXmmRegisterOperand(a, b);
1010}
1011
1012
Aart Bik18ba1212016-08-01 14:11:20 -07001013void X86Assembler::comiss(XmmRegister a, const Address& b) {
1014 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1015 EmitUint8(0x0F);
1016 EmitUint8(0x2F);
1017 EmitOperand(a, b);
1018}
1019
1020
Ian Rogers2c8f6532011-09-02 17:16:34 -07001021void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001022 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1023 EmitUint8(0x66);
1024 EmitUint8(0x0F);
1025 EmitUint8(0x2F);
1026 EmitXmmRegisterOperand(a, b);
1027}
1028
1029
Aart Bik18ba1212016-08-01 14:11:20 -07001030void X86Assembler::comisd(XmmRegister a, const Address& b) {
1031 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1032 EmitUint8(0x66);
1033 EmitUint8(0x0F);
1034 EmitUint8(0x2F);
1035 EmitOperand(a, b);
1036}
1037
1038
Calin Juravleddb7df22014-11-25 20:56:51 +00001039void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1040 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1041 EmitUint8(0x0F);
1042 EmitUint8(0x2E);
1043 EmitXmmRegisterOperand(a, b);
1044}
1045
1046
Mark Mendell9f51f262015-10-30 09:21:37 -04001047void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1048 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1049 EmitUint8(0x0F);
1050 EmitUint8(0x2E);
1051 EmitOperand(a, b);
1052}
1053
1054
Calin Juravleddb7df22014-11-25 20:56:51 +00001055void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1056 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1057 EmitUint8(0x66);
1058 EmitUint8(0x0F);
1059 EmitUint8(0x2E);
1060 EmitXmmRegisterOperand(a, b);
1061}
1062
1063
Mark Mendell9f51f262015-10-30 09:21:37 -04001064void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1065 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1066 EmitUint8(0x66);
1067 EmitUint8(0x0F);
1068 EmitUint8(0x2E);
1069 EmitOperand(a, b);
1070}
1071
1072
Mark Mendellfb8d2792015-03-31 22:16:59 -04001073void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1074 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1075 EmitUint8(0x66);
1076 EmitUint8(0x0F);
1077 EmitUint8(0x3A);
1078 EmitUint8(0x0B);
1079 EmitXmmRegisterOperand(dst, src);
1080 EmitUint8(imm.value());
1081}
1082
1083
1084void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1085 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1086 EmitUint8(0x66);
1087 EmitUint8(0x0F);
1088 EmitUint8(0x3A);
1089 EmitUint8(0x0A);
1090 EmitXmmRegisterOperand(dst, src);
1091 EmitUint8(imm.value());
1092}
1093
1094
Ian Rogers2c8f6532011-09-02 17:16:34 -07001095void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1097 EmitUint8(0xF2);
1098 EmitUint8(0x0F);
1099 EmitUint8(0x51);
1100 EmitXmmRegisterOperand(dst, src);
1101}
1102
1103
Ian Rogers2c8f6532011-09-02 17:16:34 -07001104void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001105 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1106 EmitUint8(0xF3);
1107 EmitUint8(0x0F);
1108 EmitUint8(0x51);
1109 EmitXmmRegisterOperand(dst, src);
1110}
1111
1112
Ian Rogers2c8f6532011-09-02 17:16:34 -07001113void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1115 EmitUint8(0x66);
1116 EmitUint8(0x0F);
1117 EmitUint8(0x57);
1118 EmitOperand(dst, src);
1119}
1120
1121
Ian Rogers2c8f6532011-09-02 17:16:34 -07001122void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001123 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1124 EmitUint8(0x66);
1125 EmitUint8(0x0F);
1126 EmitUint8(0x57);
1127 EmitXmmRegisterOperand(dst, src);
1128}
1129
1130
Aart Bik68555e92017-02-13 14:28:45 -08001131void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001132 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1133 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001134 EmitUint8(0x57);
1135 EmitOperand(dst, src);
1136}
1137
1138
1139void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1140 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1141 EmitUint8(0x0F);
1142 EmitUint8(0x57);
1143 EmitXmmRegisterOperand(dst, src);
1144}
1145
1146
1147void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1149 EmitUint8(0x66);
1150 EmitUint8(0x0F);
1151 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001152 EmitXmmRegisterOperand(dst, src);
1153}
1154
1155
1156void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1157 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1158 EmitUint8(0x66);
1159 EmitUint8(0x0F);
1160 EmitUint8(0x54);
1161 EmitXmmRegisterOperand(dst, src);
1162}
1163
1164
Aart Bik68555e92017-02-13 14:28:45 -08001165void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001166 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1167 EmitUint8(0x66);
1168 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001169 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001170 EmitOperand(dst, src);
1171}
1172
1173
Aart Bik68555e92017-02-13 14:28:45 -08001174void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001175 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1176 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001177 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001178 EmitXmmRegisterOperand(dst, src);
1179}
1180
1181
Mark Mendell09ed1a32015-03-25 08:30:06 -04001182void X86Assembler::andps(XmmRegister dst, const Address& src) {
1183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1184 EmitUint8(0x0F);
1185 EmitUint8(0x54);
1186 EmitOperand(dst, src);
1187}
1188
1189
Aart Bik68555e92017-02-13 14:28:45 -08001190void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001191 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1192 EmitUint8(0x66);
1193 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001194 EmitUint8(0xDB);
1195 EmitXmmRegisterOperand(dst, src);
1196}
1197
1198
Aart Bik21c580b2017-03-13 11:52:07 -07001199void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
1200 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1201 EmitUint8(0x66);
1202 EmitUint8(0x0F);
1203 EmitUint8(0x55);
1204 EmitXmmRegisterOperand(dst, src);
1205}
1206
1207
1208void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
1209 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1210 EmitUint8(0x0F);
1211 EmitUint8(0x55);
1212 EmitXmmRegisterOperand(dst, src);
1213}
1214
1215
1216void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
1217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1218 EmitUint8(0x66);
1219 EmitUint8(0x0F);
1220 EmitUint8(0xDF);
1221 EmitXmmRegisterOperand(dst, src);
1222}
1223
1224
Aart Bik68555e92017-02-13 14:28:45 -08001225void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1226 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1227 EmitUint8(0x66);
1228 EmitUint8(0x0F);
1229 EmitUint8(0x56);
1230 EmitXmmRegisterOperand(dst, src);
1231}
1232
1233
1234void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1235 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1236 EmitUint8(0x0F);
1237 EmitUint8(0x56);
1238 EmitXmmRegisterOperand(dst, src);
1239}
1240
1241
1242void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1244 EmitUint8(0x66);
1245 EmitUint8(0x0F);
1246 EmitUint8(0xEB);
1247 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001248}
1249
1250
Aart Bik67d3fd72017-03-31 15:11:53 -07001251void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
1252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1253 EmitUint8(0x66);
1254 EmitUint8(0x0F);
1255 EmitUint8(0xE0);
1256 EmitXmmRegisterOperand(dst, src);
1257}
1258
1259
1260void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
1261 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262 EmitUint8(0x66);
1263 EmitUint8(0x0F);
1264 EmitUint8(0xE3);
1265 EmitXmmRegisterOperand(dst, src);
1266}
1267
Aart Bik6005a872017-07-24 13:33:39 -07001268
1269void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
1270 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1271 EmitUint8(0x66);
1272 EmitUint8(0x0F);
1273 EmitUint8(0xF6);
1274 EmitXmmRegisterOperand(dst, src);
1275}
1276
1277
1278void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
1279 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1280 EmitUint8(0x66);
1281 EmitUint8(0x0F);
1282 EmitUint8(0xF5);
1283 EmitXmmRegisterOperand(dst, src);
1284}
1285
1286
1287void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
1288 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1289 EmitUint8(0x66);
1290 EmitUint8(0x0F);
1291 EmitUint8(0x38);
1292 EmitUint8(0x01);
1293 EmitXmmRegisterOperand(dst, src);
1294}
1295
1296
1297void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
1298 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1299 EmitUint8(0x66);
1300 EmitUint8(0x0F);
1301 EmitUint8(0x38);
1302 EmitUint8(0x02);
1303 EmitXmmRegisterOperand(dst, src);
1304}
1305
1306
1307void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
1308 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1309 EmitUint8(0xF2);
1310 EmitUint8(0x0F);
1311 EmitUint8(0x7C);
1312 EmitXmmRegisterOperand(dst, src);
1313}
1314
1315
1316void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
1317 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1318 EmitUint8(0x66);
1319 EmitUint8(0x0F);
1320 EmitUint8(0x7C);
1321 EmitXmmRegisterOperand(dst, src);
1322}
1323
1324
1325void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
1326 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1327 EmitUint8(0x66);
1328 EmitUint8(0x0F);
1329 EmitUint8(0x38);
1330 EmitUint8(0x05);
1331 EmitXmmRegisterOperand(dst, src);
1332}
1333
1334
1335void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
1336 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1337 EmitUint8(0x66);
1338 EmitUint8(0x0F);
1339 EmitUint8(0x38);
1340 EmitUint8(0x06);
1341 EmitXmmRegisterOperand(dst, src);
1342}
1343
1344
1345void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
1346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1347 EmitUint8(0xF2);
1348 EmitUint8(0x0F);
1349 EmitUint8(0x7D);
1350 EmitXmmRegisterOperand(dst, src);
1351}
1352
1353
1354void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
1355 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1356 EmitUint8(0x66);
1357 EmitUint8(0x0F);
1358 EmitUint8(0x7D);
1359 EmitXmmRegisterOperand(dst, src);
1360}
1361
1362
Aart Bikc8e93c72017-05-10 10:49:22 -07001363void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
1364 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1365 EmitUint8(0x66);
1366 EmitUint8(0x0F);
1367 EmitUint8(0x38);
1368 EmitUint8(0x38);
1369 EmitXmmRegisterOperand(dst, src);
1370}
1371
1372void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
1373 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1374 EmitUint8(0x66);
1375 EmitUint8(0x0F);
1376 EmitUint8(0x38);
1377 EmitUint8(0x3C);
1378 EmitXmmRegisterOperand(dst, src);
1379}
1380
1381void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
1382 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1383 EmitUint8(0x66);
1384 EmitUint8(0x0F);
1385 EmitUint8(0xEA);
1386 EmitXmmRegisterOperand(dst, src);
1387}
1388
1389void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
1390 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1391 EmitUint8(0x66);
1392 EmitUint8(0x0F);
1393 EmitUint8(0xEE);
1394 EmitXmmRegisterOperand(dst, src);
1395}
1396
1397void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
1398 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1399 EmitUint8(0x66);
1400 EmitUint8(0x0F);
1401 EmitUint8(0x38);
1402 EmitUint8(0x39);
1403 EmitXmmRegisterOperand(dst, src);
1404}
1405
1406void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
1407 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1408 EmitUint8(0x66);
1409 EmitUint8(0x0F);
1410 EmitUint8(0x38);
1411 EmitUint8(0x3D);
1412 EmitXmmRegisterOperand(dst, src);
1413}
1414
1415void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
1416 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1417 EmitUint8(0x66);
1418 EmitUint8(0x0F);
1419 EmitUint8(0xDA);
1420 EmitXmmRegisterOperand(dst, src);
1421}
1422
1423void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
1424 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1425 EmitUint8(0x66);
1426 EmitUint8(0x0F);
1427 EmitUint8(0xDE);
1428 EmitXmmRegisterOperand(dst, src);
1429}
1430
1431void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
1432 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1433 EmitUint8(0x66);
1434 EmitUint8(0x0F);
1435 EmitUint8(0x38);
1436 EmitUint8(0x3A);
1437 EmitXmmRegisterOperand(dst, src);
1438}
1439
1440void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
1441 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1442 EmitUint8(0x66);
1443 EmitUint8(0x0F);
1444 EmitUint8(0x38);
1445 EmitUint8(0x3E);
1446 EmitXmmRegisterOperand(dst, src);
1447}
1448
1449void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
1450 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1451 EmitUint8(0x66);
1452 EmitUint8(0x0F);
1453 EmitUint8(0x38);
1454 EmitUint8(0x3B);
1455 EmitXmmRegisterOperand(dst, src);
1456}
1457
1458void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
1459 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1460 EmitUint8(0x66);
1461 EmitUint8(0x0F);
1462 EmitUint8(0x38);
1463 EmitUint8(0x3F);
1464 EmitXmmRegisterOperand(dst, src);
1465}
1466
1467void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
1468 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1469 EmitUint8(0x0F);
1470 EmitUint8(0x5D);
1471 EmitXmmRegisterOperand(dst, src);
1472}
1473
1474void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
1475 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1476 EmitUint8(0x0F);
1477 EmitUint8(0x5F);
1478 EmitXmmRegisterOperand(dst, src);
1479}
1480
1481void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
1482 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1483 EmitUint8(0x66);
1484 EmitUint8(0x0F);
1485 EmitUint8(0x5D);
1486 EmitXmmRegisterOperand(dst, src);
1487}
1488
1489void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
1490 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1491 EmitUint8(0x66);
1492 EmitUint8(0x0F);
1493 EmitUint8(0x5F);
1494 EmitXmmRegisterOperand(dst, src);
1495}
Aart Bik67d3fd72017-03-31 15:11:53 -07001496
Aart Bik4b455332017-03-15 11:19:35 -07001497void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
1498 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1499 EmitUint8(0x66);
1500 EmitUint8(0x0F);
1501 EmitUint8(0x74);
1502 EmitXmmRegisterOperand(dst, src);
1503}
1504
1505
1506void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
1507 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1508 EmitUint8(0x66);
1509 EmitUint8(0x0F);
1510 EmitUint8(0x75);
1511 EmitXmmRegisterOperand(dst, src);
1512}
1513
1514
1515void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
1516 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1517 EmitUint8(0x66);
1518 EmitUint8(0x0F);
1519 EmitUint8(0x76);
1520 EmitXmmRegisterOperand(dst, src);
1521}
1522
1523
1524void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
1525 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1526 EmitUint8(0x66);
1527 EmitUint8(0x0F);
1528 EmitUint8(0x38);
1529 EmitUint8(0x29);
1530 EmitXmmRegisterOperand(dst, src);
1531}
1532
1533
Aart Bik8939c642017-04-03 14:09:01 -07001534void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
1535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1536 EmitUint8(0x66);
1537 EmitUint8(0x0F);
1538 EmitUint8(0x64);
1539 EmitXmmRegisterOperand(dst, src);
1540}
1541
1542
1543void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
1544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1545 EmitUint8(0x66);
1546 EmitUint8(0x0F);
1547 EmitUint8(0x65);
1548 EmitXmmRegisterOperand(dst, src);
1549}
1550
1551
1552void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
1553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1554 EmitUint8(0x66);
1555 EmitUint8(0x0F);
1556 EmitUint8(0x66);
1557 EmitXmmRegisterOperand(dst, src);
1558}
1559
1560
1561void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
1562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1563 EmitUint8(0x66);
1564 EmitUint8(0x0F);
1565 EmitUint8(0x38);
1566 EmitUint8(0x37);
1567 EmitXmmRegisterOperand(dst, src);
1568}
1569
1570
Aart Bik12e06ed2017-01-31 16:11:24 -08001571void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1572 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1573 EmitUint8(0x66);
1574 EmitUint8(0x0F);
1575 EmitUint8(0xC6);
1576 EmitXmmRegisterOperand(dst, src);
1577 EmitUint8(imm.value());
1578}
1579
1580
1581void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1582 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1583 EmitUint8(0x0F);
1584 EmitUint8(0xC6);
1585 EmitXmmRegisterOperand(dst, src);
1586 EmitUint8(imm.value());
1587}
1588
1589
Aart Bik68555e92017-02-13 14:28:45 -08001590void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1591 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1592 EmitUint8(0x66);
1593 EmitUint8(0x0F);
1594 EmitUint8(0x70);
1595 EmitXmmRegisterOperand(dst, src);
1596 EmitUint8(imm.value());
1597}
1598
1599
Aart Bike69d7a92017-02-17 11:48:23 -08001600void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1602 EmitUint8(0x66);
1603 EmitUint8(0x0F);
1604 EmitUint8(0x60);
1605 EmitXmmRegisterOperand(dst, src);
1606}
1607
1608
1609void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1611 EmitUint8(0x66);
1612 EmitUint8(0x0F);
1613 EmitUint8(0x61);
1614 EmitXmmRegisterOperand(dst, src);
1615}
1616
1617
1618void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1620 EmitUint8(0x66);
1621 EmitUint8(0x0F);
1622 EmitUint8(0x62);
1623 EmitXmmRegisterOperand(dst, src);
1624}
1625
1626
1627void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1629 EmitUint8(0x66);
1630 EmitUint8(0x0F);
1631 EmitUint8(0x6C);
1632 EmitXmmRegisterOperand(dst, src);
1633}
1634
1635
Aart Bik3332db82017-08-11 15:10:30 -07001636void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
1637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1638 EmitUint8(0x66);
1639 EmitUint8(0x0F);
1640 EmitUint8(0x68);
1641 EmitXmmRegisterOperand(dst, src);
1642}
1643
1644
1645void X86Assembler::punpckhwd(XmmRegister dst, XmmRegister src) {
1646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1647 EmitUint8(0x66);
1648 EmitUint8(0x0F);
1649 EmitUint8(0x69);
1650 EmitXmmRegisterOperand(dst, src);
1651}
1652
1653
1654void X86Assembler::punpckhdq(XmmRegister dst, XmmRegister src) {
1655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1656 EmitUint8(0x66);
1657 EmitUint8(0x0F);
1658 EmitUint8(0x6A);
1659 EmitXmmRegisterOperand(dst, src);
1660}
1661
1662
1663void X86Assembler::punpckhqdq(XmmRegister dst, XmmRegister src) {
1664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1665 EmitUint8(0x66);
1666 EmitUint8(0x0F);
1667 EmitUint8(0x6D);
1668 EmitXmmRegisterOperand(dst, src);
1669}
1670
1671
Aart Bike69d7a92017-02-17 11:48:23 -08001672void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1673 DCHECK(shift_count.is_uint8());
1674 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1675 EmitUint8(0x66);
1676 EmitUint8(0x0F);
1677 EmitUint8(0x71);
1678 EmitXmmRegisterOperand(6, reg);
1679 EmitUint8(shift_count.value());
1680}
1681
1682
1683void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1684 DCHECK(shift_count.is_uint8());
1685 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1686 EmitUint8(0x66);
1687 EmitUint8(0x0F);
1688 EmitUint8(0x72);
1689 EmitXmmRegisterOperand(6, reg);
1690 EmitUint8(shift_count.value());
1691}
1692
1693
1694void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1695 DCHECK(shift_count.is_uint8());
1696 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1697 EmitUint8(0x66);
1698 EmitUint8(0x0F);
1699 EmitUint8(0x73);
1700 EmitXmmRegisterOperand(6, reg);
1701 EmitUint8(shift_count.value());
1702}
1703
1704
1705void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1706 DCHECK(shift_count.is_uint8());
1707 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1708 EmitUint8(0x66);
1709 EmitUint8(0x0F);
1710 EmitUint8(0x71);
1711 EmitXmmRegisterOperand(4, reg);
1712 EmitUint8(shift_count.value());
1713}
1714
1715
1716void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1717 DCHECK(shift_count.is_uint8());
1718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1719 EmitUint8(0x66);
1720 EmitUint8(0x0F);
1721 EmitUint8(0x72);
1722 EmitXmmRegisterOperand(4, reg);
1723 EmitUint8(shift_count.value());
1724}
1725
1726
1727void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1728 DCHECK(shift_count.is_uint8());
1729 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1730 EmitUint8(0x66);
1731 EmitUint8(0x0F);
1732 EmitUint8(0x71);
1733 EmitXmmRegisterOperand(2, reg);
1734 EmitUint8(shift_count.value());
1735}
1736
1737
1738void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1739 DCHECK(shift_count.is_uint8());
1740 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1741 EmitUint8(0x66);
1742 EmitUint8(0x0F);
1743 EmitUint8(0x72);
1744 EmitXmmRegisterOperand(2, reg);
1745 EmitUint8(shift_count.value());
1746}
1747
1748
1749void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1750 DCHECK(shift_count.is_uint8());
1751 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1752 EmitUint8(0x66);
1753 EmitUint8(0x0F);
1754 EmitUint8(0x73);
1755 EmitXmmRegisterOperand(2, reg);
1756 EmitUint8(shift_count.value());
1757}
1758
1759
1760void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1761 DCHECK(shift_count.is_uint8());
1762 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1763 EmitUint8(0x66);
1764 EmitUint8(0x0F);
1765 EmitUint8(0x73);
1766 EmitXmmRegisterOperand(3, reg);
1767 EmitUint8(shift_count.value());
1768}
1769
1770
Ian Rogers2c8f6532011-09-02 17:16:34 -07001771void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1773 EmitUint8(0xDD);
1774 EmitOperand(0, src);
1775}
1776
1777
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001778void X86Assembler::fstl(const Address& dst) {
1779 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1780 EmitUint8(0xDD);
1781 EmitOperand(2, dst);
1782}
1783
1784
Ian Rogers2c8f6532011-09-02 17:16:34 -07001785void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001786 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1787 EmitUint8(0xDD);
1788 EmitOperand(3, dst);
1789}
1790
1791
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001792void X86Assembler::fstsw() {
1793 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1794 EmitUint8(0x9B);
1795 EmitUint8(0xDF);
1796 EmitUint8(0xE0);
1797}
1798
1799
Ian Rogers2c8f6532011-09-02 17:16:34 -07001800void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001801 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1802 EmitUint8(0xD9);
1803 EmitOperand(7, dst);
1804}
1805
1806
Ian Rogers2c8f6532011-09-02 17:16:34 -07001807void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1809 EmitUint8(0xD9);
1810 EmitOperand(5, src);
1811}
1812
1813
Ian Rogers2c8f6532011-09-02 17:16:34 -07001814void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001815 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1816 EmitUint8(0xDF);
1817 EmitOperand(7, dst);
1818}
1819
1820
Ian Rogers2c8f6532011-09-02 17:16:34 -07001821void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001822 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1823 EmitUint8(0xDB);
1824 EmitOperand(3, dst);
1825}
1826
1827
Ian Rogers2c8f6532011-09-02 17:16:34 -07001828void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001829 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1830 EmitUint8(0xDF);
1831 EmitOperand(5, src);
1832}
1833
1834
Roland Levillain0a186012015-04-13 17:00:20 +01001835void X86Assembler::filds(const Address& src) {
1836 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1837 EmitUint8(0xDB);
1838 EmitOperand(0, src);
1839}
1840
1841
Ian Rogers2c8f6532011-09-02 17:16:34 -07001842void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001843 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1844 EmitUint8(0xD9);
1845 EmitUint8(0xF7);
1846}
1847
1848
Ian Rogers2c8f6532011-09-02 17:16:34 -07001849void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001850 CHECK_LT(index.value(), 7);
1851 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1852 EmitUint8(0xDD);
1853 EmitUint8(0xC0 + index.value());
1854}
1855
1856
Ian Rogers2c8f6532011-09-02 17:16:34 -07001857void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001858 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1859 EmitUint8(0xD9);
1860 EmitUint8(0xFE);
1861}
1862
1863
Ian Rogers2c8f6532011-09-02 17:16:34 -07001864void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001865 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1866 EmitUint8(0xD9);
1867 EmitUint8(0xFF);
1868}
1869
1870
Ian Rogers2c8f6532011-09-02 17:16:34 -07001871void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001872 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1873 EmitUint8(0xD9);
1874 EmitUint8(0xF2);
1875}
1876
1877
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001878void X86Assembler::fucompp() {
1879 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1880 EmitUint8(0xDA);
1881 EmitUint8(0xE9);
1882}
1883
1884
1885void X86Assembler::fprem() {
1886 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1887 EmitUint8(0xD9);
1888 EmitUint8(0xF8);
1889}
1890
1891
Ian Rogers2c8f6532011-09-02 17:16:34 -07001892void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001893 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1894 EmitUint8(0x87);
1895 EmitRegisterOperand(dst, src);
1896}
1897
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001898
Ian Rogers7caad772012-03-30 01:07:54 -07001899void X86Assembler::xchgl(Register reg, const Address& address) {
1900 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1901 EmitUint8(0x87);
1902 EmitOperand(reg, address);
1903}
1904
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001905
Serguei Katkov3b625932016-05-06 10:24:17 +06001906void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1907 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1908 EmitUint8(0x80);
1909 EmitOperand(7, address);
1910 EmitUint8(imm.value() & 0xFF);
1911}
1912
1913
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001914void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1915 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1916 EmitUint8(0x66);
Vladimir Marko29a8d842018-02-13 13:46:15 +00001917 EmitComplex(7, address, imm, /* is_16_op */ true);
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001918}
1919
1920
Ian Rogers2c8f6532011-09-02 17:16:34 -07001921void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001922 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1923 EmitComplex(7, Operand(reg), imm);
1924}
1925
1926
Ian Rogers2c8f6532011-09-02 17:16:34 -07001927void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001928 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1929 EmitUint8(0x3B);
1930 EmitOperand(reg0, Operand(reg1));
1931}
1932
1933
Ian Rogers2c8f6532011-09-02 17:16:34 -07001934void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1936 EmitUint8(0x3B);
1937 EmitOperand(reg, address);
1938}
1939
1940
Ian Rogers2c8f6532011-09-02 17:16:34 -07001941void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001942 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1943 EmitUint8(0x03);
1944 EmitRegisterOperand(dst, src);
1945}
1946
1947
Ian Rogers2c8f6532011-09-02 17:16:34 -07001948void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001949 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1950 EmitUint8(0x03);
1951 EmitOperand(reg, address);
1952}
1953
1954
Ian Rogers2c8f6532011-09-02 17:16:34 -07001955void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001956 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1957 EmitUint8(0x39);
1958 EmitOperand(reg, address);
1959}
1960
1961
Ian Rogers2c8f6532011-09-02 17:16:34 -07001962void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001963 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1964 EmitComplex(7, address, imm);
1965}
1966
1967
Ian Rogers2c8f6532011-09-02 17:16:34 -07001968void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001969 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1970 EmitUint8(0x85);
1971 EmitRegisterOperand(reg1, reg2);
1972}
1973
1974
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001975void X86Assembler::testl(Register reg, const Address& address) {
1976 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1977 EmitUint8(0x85);
1978 EmitOperand(reg, address);
1979}
1980
1981
Ian Rogers2c8f6532011-09-02 17:16:34 -07001982void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001983 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1984 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1985 // we only test the byte register to keep the encoding short.
1986 if (immediate.is_uint8() && reg < 4) {
1987 // Use zero-extended 8-bit immediate.
1988 if (reg == EAX) {
1989 EmitUint8(0xA8);
1990 } else {
1991 EmitUint8(0xF6);
1992 EmitUint8(0xC0 + reg);
1993 }
1994 EmitUint8(immediate.value() & 0xFF);
1995 } else if (reg == EAX) {
1996 // Use short form if the destination is EAX.
1997 EmitUint8(0xA9);
1998 EmitImmediate(immediate);
1999 } else {
2000 EmitUint8(0xF7);
2001 EmitOperand(0, Operand(reg));
2002 EmitImmediate(immediate);
2003 }
2004}
2005
2006
Vladimir Marko953437b2016-08-24 08:30:46 +00002007void X86Assembler::testb(const Address& dst, const Immediate& imm) {
2008 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2009 EmitUint8(0xF6);
2010 EmitOperand(EAX, dst);
2011 CHECK(imm.is_int8());
2012 EmitUint8(imm.value() & 0xFF);
2013}
2014
2015
2016void X86Assembler::testl(const Address& dst, const Immediate& imm) {
2017 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2018 EmitUint8(0xF7);
2019 EmitOperand(0, dst);
2020 EmitImmediate(imm);
2021}
2022
2023
Ian Rogers2c8f6532011-09-02 17:16:34 -07002024void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002025 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2026 EmitUint8(0x23);
2027 EmitOperand(dst, Operand(src));
2028}
2029
2030
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002031void X86Assembler::andl(Register reg, const Address& address) {
2032 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2033 EmitUint8(0x23);
2034 EmitOperand(reg, address);
2035}
2036
2037
Ian Rogers2c8f6532011-09-02 17:16:34 -07002038void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002039 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2040 EmitComplex(4, Operand(dst), imm);
2041}
2042
2043
Ian Rogers2c8f6532011-09-02 17:16:34 -07002044void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002045 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2046 EmitUint8(0x0B);
2047 EmitOperand(dst, Operand(src));
2048}
2049
2050
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002051void X86Assembler::orl(Register reg, const Address& address) {
2052 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2053 EmitUint8(0x0B);
2054 EmitOperand(reg, address);
2055}
2056
2057
Ian Rogers2c8f6532011-09-02 17:16:34 -07002058void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002059 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2060 EmitComplex(1, Operand(dst), imm);
2061}
2062
2063
Ian Rogers2c8f6532011-09-02 17:16:34 -07002064void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002065 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2066 EmitUint8(0x33);
2067 EmitOperand(dst, Operand(src));
2068}
2069
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002070
2071void X86Assembler::xorl(Register reg, const Address& address) {
2072 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2073 EmitUint8(0x33);
2074 EmitOperand(reg, address);
2075}
2076
2077
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01002078void X86Assembler::xorl(Register dst, const Immediate& imm) {
2079 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2080 EmitComplex(6, Operand(dst), imm);
2081}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002082
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002083
Ian Rogers2c8f6532011-09-02 17:16:34 -07002084void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002085 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2086 EmitComplex(0, Operand(reg), imm);
2087}
2088
2089
Ian Rogers2c8f6532011-09-02 17:16:34 -07002090void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002091 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2092 EmitUint8(0x01);
2093 EmitOperand(reg, address);
2094}
2095
2096
Ian Rogers2c8f6532011-09-02 17:16:34 -07002097void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002098 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2099 EmitComplex(0, address, imm);
2100}
2101
2102
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002103void X86Assembler::addw(const Address& address, const Immediate& imm) {
2104 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2105 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
2106 EmitUint8(0x66);
2107 EmitComplex(0, address, imm, /* is_16_op */ true);
2108}
2109
2110
Ian Rogers2c8f6532011-09-02 17:16:34 -07002111void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002112 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2113 EmitComplex(2, Operand(reg), imm);
2114}
2115
2116
Ian Rogers2c8f6532011-09-02 17:16:34 -07002117void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002118 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2119 EmitUint8(0x13);
2120 EmitOperand(dst, Operand(src));
2121}
2122
2123
Ian Rogers2c8f6532011-09-02 17:16:34 -07002124void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002125 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2126 EmitUint8(0x13);
2127 EmitOperand(dst, address);
2128}
2129
2130
Ian Rogers2c8f6532011-09-02 17:16:34 -07002131void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002132 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2133 EmitUint8(0x2B);
2134 EmitOperand(dst, Operand(src));
2135}
2136
2137
Ian Rogers2c8f6532011-09-02 17:16:34 -07002138void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002139 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2140 EmitComplex(5, Operand(reg), imm);
2141}
2142
2143
Ian Rogers2c8f6532011-09-02 17:16:34 -07002144void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002145 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2146 EmitUint8(0x2B);
2147 EmitOperand(reg, address);
2148}
2149
2150
Mark Mendell09ed1a32015-03-25 08:30:06 -04002151void X86Assembler::subl(const Address& address, Register reg) {
2152 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2153 EmitUint8(0x29);
2154 EmitOperand(reg, address);
2155}
2156
2157
Ian Rogers2c8f6532011-09-02 17:16:34 -07002158void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002159 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2160 EmitUint8(0x99);
2161}
2162
2163
Ian Rogers2c8f6532011-09-02 17:16:34 -07002164void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002165 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2166 EmitUint8(0xF7);
2167 EmitUint8(0xF8 | reg);
2168}
2169
2170
Ian Rogers2c8f6532011-09-02 17:16:34 -07002171void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002172 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2173 EmitUint8(0x0F);
2174 EmitUint8(0xAF);
2175 EmitOperand(dst, Operand(src));
2176}
2177
2178
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002179void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002180 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002181 // See whether imm can be represented as a sign-extended 8bit value.
2182 int32_t v32 = static_cast<int32_t>(imm.value());
2183 if (IsInt<8>(v32)) {
2184 // Sign-extension works.
2185 EmitUint8(0x6B);
2186 EmitOperand(dst, Operand(src));
2187 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
2188 } else {
2189 // Not representable, use full immediate.
2190 EmitUint8(0x69);
2191 EmitOperand(dst, Operand(src));
2192 EmitImmediate(imm);
2193 }
2194}
2195
2196
2197void X86Assembler::imull(Register reg, const Immediate& imm) {
2198 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002199}
2200
2201
Ian Rogers2c8f6532011-09-02 17:16:34 -07002202void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2204 EmitUint8(0x0F);
2205 EmitUint8(0xAF);
2206 EmitOperand(reg, address);
2207}
2208
2209
Ian Rogers2c8f6532011-09-02 17:16:34 -07002210void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002211 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2212 EmitUint8(0xF7);
2213 EmitOperand(5, Operand(reg));
2214}
2215
2216
Ian Rogers2c8f6532011-09-02 17:16:34 -07002217void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002218 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2219 EmitUint8(0xF7);
2220 EmitOperand(5, address);
2221}
2222
2223
Ian Rogers2c8f6532011-09-02 17:16:34 -07002224void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2226 EmitUint8(0xF7);
2227 EmitOperand(4, Operand(reg));
2228}
2229
2230
Ian Rogers2c8f6532011-09-02 17:16:34 -07002231void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002232 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2233 EmitUint8(0xF7);
2234 EmitOperand(4, address);
2235}
2236
2237
Ian Rogers2c8f6532011-09-02 17:16:34 -07002238void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002239 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2240 EmitUint8(0x1B);
2241 EmitOperand(dst, Operand(src));
2242}
2243
2244
Ian Rogers2c8f6532011-09-02 17:16:34 -07002245void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002246 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2247 EmitComplex(3, Operand(reg), imm);
2248}
2249
2250
Ian Rogers2c8f6532011-09-02 17:16:34 -07002251void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2253 EmitUint8(0x1B);
2254 EmitOperand(dst, address);
2255}
2256
2257
Mark Mendell09ed1a32015-03-25 08:30:06 -04002258void X86Assembler::sbbl(const Address& address, Register src) {
2259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2260 EmitUint8(0x19);
2261 EmitOperand(src, address);
2262}
2263
2264
Ian Rogers2c8f6532011-09-02 17:16:34 -07002265void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002266 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2267 EmitUint8(0x40 + reg);
2268}
2269
2270
Ian Rogers2c8f6532011-09-02 17:16:34 -07002271void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002272 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2273 EmitUint8(0xFF);
2274 EmitOperand(0, address);
2275}
2276
2277
Ian Rogers2c8f6532011-09-02 17:16:34 -07002278void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002279 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2280 EmitUint8(0x48 + reg);
2281}
2282
2283
Ian Rogers2c8f6532011-09-02 17:16:34 -07002284void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002285 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2286 EmitUint8(0xFF);
2287 EmitOperand(1, address);
2288}
2289
2290
Ian Rogers2c8f6532011-09-02 17:16:34 -07002291void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002292 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002293}
2294
2295
Ian Rogers2c8f6532011-09-02 17:16:34 -07002296void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002297 EmitGenericShift(4, Operand(operand), shifter);
2298}
2299
2300
2301void X86Assembler::shll(const Address& address, const Immediate& imm) {
2302 EmitGenericShift(4, address, imm);
2303}
2304
2305
2306void X86Assembler::shll(const Address& address, Register shifter) {
2307 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002308}
2309
2310
Ian Rogers2c8f6532011-09-02 17:16:34 -07002311void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002312 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002313}
2314
2315
Ian Rogers2c8f6532011-09-02 17:16:34 -07002316void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002317 EmitGenericShift(5, Operand(operand), shifter);
2318}
2319
2320
2321void X86Assembler::shrl(const Address& address, const Immediate& imm) {
2322 EmitGenericShift(5, address, imm);
2323}
2324
2325
2326void X86Assembler::shrl(const Address& address, Register shifter) {
2327 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002328}
2329
2330
Ian Rogers2c8f6532011-09-02 17:16:34 -07002331void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002332 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002333}
2334
2335
Ian Rogers2c8f6532011-09-02 17:16:34 -07002336void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002337 EmitGenericShift(7, Operand(operand), shifter);
2338}
2339
2340
2341void X86Assembler::sarl(const Address& address, const Immediate& imm) {
2342 EmitGenericShift(7, address, imm);
2343}
2344
2345
2346void X86Assembler::sarl(const Address& address, Register shifter) {
2347 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002348}
2349
2350
Calin Juravle9aec02f2014-11-18 23:06:35 +00002351void X86Assembler::shld(Register dst, Register src, Register shifter) {
2352 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002353 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2354 EmitUint8(0x0F);
2355 EmitUint8(0xA5);
2356 EmitRegisterOperand(src, dst);
2357}
2358
2359
Mark P Mendell73945692015-04-29 14:56:17 +00002360void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
2361 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2362 EmitUint8(0x0F);
2363 EmitUint8(0xA4);
2364 EmitRegisterOperand(src, dst);
2365 EmitUint8(imm.value() & 0xFF);
2366}
2367
2368
Calin Juravle9aec02f2014-11-18 23:06:35 +00002369void X86Assembler::shrd(Register dst, Register src, Register shifter) {
2370 DCHECK_EQ(ECX, shifter);
2371 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2372 EmitUint8(0x0F);
2373 EmitUint8(0xAD);
2374 EmitRegisterOperand(src, dst);
2375}
2376
2377
Mark P Mendell73945692015-04-29 14:56:17 +00002378void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
2379 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2380 EmitUint8(0x0F);
2381 EmitUint8(0xAC);
2382 EmitRegisterOperand(src, dst);
2383 EmitUint8(imm.value() & 0xFF);
2384}
2385
2386
Mark Mendellbcee0922015-09-15 21:45:01 -04002387void X86Assembler::roll(Register reg, const Immediate& imm) {
2388 EmitGenericShift(0, Operand(reg), imm);
2389}
2390
2391
2392void X86Assembler::roll(Register operand, Register shifter) {
2393 EmitGenericShift(0, Operand(operand), shifter);
2394}
2395
2396
2397void X86Assembler::rorl(Register reg, const Immediate& imm) {
2398 EmitGenericShift(1, Operand(reg), imm);
2399}
2400
2401
2402void X86Assembler::rorl(Register operand, Register shifter) {
2403 EmitGenericShift(1, Operand(operand), shifter);
2404}
2405
2406
Ian Rogers2c8f6532011-09-02 17:16:34 -07002407void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002408 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2409 EmitUint8(0xF7);
2410 EmitOperand(3, Operand(reg));
2411}
2412
2413
Ian Rogers2c8f6532011-09-02 17:16:34 -07002414void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002415 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2416 EmitUint8(0xF7);
2417 EmitUint8(0xD0 | reg);
2418}
2419
2420
Ian Rogers2c8f6532011-09-02 17:16:34 -07002421void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2423 EmitUint8(0xC8);
2424 CHECK(imm.is_uint16());
2425 EmitUint8(imm.value() & 0xFF);
2426 EmitUint8((imm.value() >> 8) & 0xFF);
2427 EmitUint8(0x00);
2428}
2429
2430
Ian Rogers2c8f6532011-09-02 17:16:34 -07002431void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002432 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2433 EmitUint8(0xC9);
2434}
2435
2436
Ian Rogers2c8f6532011-09-02 17:16:34 -07002437void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002438 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2439 EmitUint8(0xC3);
2440}
2441
2442
Ian Rogers2c8f6532011-09-02 17:16:34 -07002443void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002444 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2445 EmitUint8(0xC2);
2446 CHECK(imm.is_uint16());
2447 EmitUint8(imm.value() & 0xFF);
2448 EmitUint8((imm.value() >> 8) & 0xFF);
2449}
2450
2451
2452
Ian Rogers2c8f6532011-09-02 17:16:34 -07002453void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002454 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2455 EmitUint8(0x90);
2456}
2457
2458
Ian Rogers2c8f6532011-09-02 17:16:34 -07002459void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002460 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2461 EmitUint8(0xCC);
2462}
2463
2464
Ian Rogers2c8f6532011-09-02 17:16:34 -07002465void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002466 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2467 EmitUint8(0xF4);
2468}
2469
2470
Ian Rogers2c8f6532011-09-02 17:16:34 -07002471void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002472 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2473 if (label->IsBound()) {
2474 static const int kShortSize = 2;
2475 static const int kLongSize = 6;
2476 int offset = label->Position() - buffer_.Size();
2477 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002478 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002479 EmitUint8(0x70 + condition);
2480 EmitUint8((offset - kShortSize) & 0xFF);
2481 } else {
2482 EmitUint8(0x0F);
2483 EmitUint8(0x80 + condition);
2484 EmitInt32(offset - kLongSize);
2485 }
2486 } else {
2487 EmitUint8(0x0F);
2488 EmitUint8(0x80 + condition);
2489 EmitLabelLink(label);
2490 }
2491}
2492
2493
Mark Mendell73f455e2015-08-21 09:30:05 -04002494void X86Assembler::j(Condition condition, NearLabel* label) {
2495 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2496 if (label->IsBound()) {
2497 static const int kShortSize = 2;
2498 int offset = label->Position() - buffer_.Size();
2499 CHECK_LE(offset, 0);
2500 CHECK(IsInt<8>(offset - kShortSize));
2501 EmitUint8(0x70 + condition);
2502 EmitUint8((offset - kShortSize) & 0xFF);
2503 } else {
2504 EmitUint8(0x70 + condition);
2505 EmitLabelLink(label);
2506 }
2507}
2508
2509
2510void X86Assembler::jecxz(NearLabel* label) {
2511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2512 if (label->IsBound()) {
2513 static const int kShortSize = 2;
2514 int offset = label->Position() - buffer_.Size();
2515 CHECK_LE(offset, 0);
2516 CHECK(IsInt<8>(offset - kShortSize));
2517 EmitUint8(0xE3);
2518 EmitUint8((offset - kShortSize) & 0xFF);
2519 } else {
2520 EmitUint8(0xE3);
2521 EmitLabelLink(label);
2522 }
2523}
2524
2525
Ian Rogers2c8f6532011-09-02 17:16:34 -07002526void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2528 EmitUint8(0xFF);
2529 EmitRegisterOperand(4, reg);
2530}
2531
Ian Rogers7caad772012-03-30 01:07:54 -07002532void X86Assembler::jmp(const Address& address) {
2533 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2534 EmitUint8(0xFF);
2535 EmitOperand(4, address);
2536}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002537
Ian Rogers2c8f6532011-09-02 17:16:34 -07002538void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002539 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2540 if (label->IsBound()) {
2541 static const int kShortSize = 2;
2542 static const int kLongSize = 5;
2543 int offset = label->Position() - buffer_.Size();
2544 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002545 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002546 EmitUint8(0xEB);
2547 EmitUint8((offset - kShortSize) & 0xFF);
2548 } else {
2549 EmitUint8(0xE9);
2550 EmitInt32(offset - kLongSize);
2551 }
2552 } else {
2553 EmitUint8(0xE9);
2554 EmitLabelLink(label);
2555 }
2556}
2557
2558
Mark Mendell73f455e2015-08-21 09:30:05 -04002559void X86Assembler::jmp(NearLabel* label) {
2560 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2561 if (label->IsBound()) {
2562 static const int kShortSize = 2;
2563 int offset = label->Position() - buffer_.Size();
2564 CHECK_LE(offset, 0);
2565 CHECK(IsInt<8>(offset - kShortSize));
2566 EmitUint8(0xEB);
2567 EmitUint8((offset - kShortSize) & 0xFF);
2568 } else {
2569 EmitUint8(0xEB);
2570 EmitLabelLink(label);
2571 }
2572}
2573
2574
jessicahandojob03d6402016-09-07 12:16:53 -07002575void X86Assembler::repne_scasb() {
2576 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2577 EmitUint8(0xF2);
2578 EmitUint8(0xAE);
2579}
2580
2581
Andreas Gampe21030dd2015-05-07 14:46:15 -07002582void X86Assembler::repne_scasw() {
2583 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2584 EmitUint8(0x66);
2585 EmitUint8(0xF2);
2586 EmitUint8(0xAF);
2587}
2588
2589
jessicahandojob03d6402016-09-07 12:16:53 -07002590void X86Assembler::repe_cmpsb() {
2591 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2592 EmitUint8(0xF2);
2593 EmitUint8(0xA6);
2594}
2595
2596
agicsaki71311f82015-07-27 11:34:13 -07002597void X86Assembler::repe_cmpsw() {
2598 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2599 EmitUint8(0x66);
2600 EmitUint8(0xF3);
2601 EmitUint8(0xA7);
2602}
2603
2604
agicsaki970abfb2015-07-31 10:31:14 -07002605void X86Assembler::repe_cmpsl() {
2606 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2607 EmitUint8(0xF3);
2608 EmitUint8(0xA7);
2609}
2610
2611
jessicahandojob03d6402016-09-07 12:16:53 -07002612void X86Assembler::rep_movsb() {
2613 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2614 EmitUint8(0xF3);
2615 EmitUint8(0xA4);
2616}
2617
2618
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002619void X86Assembler::rep_movsw() {
2620 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2621 EmitUint8(0x66);
2622 EmitUint8(0xF3);
2623 EmitUint8(0xA5);
2624}
2625
2626
Ian Rogers2c8f6532011-09-02 17:16:34 -07002627X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2629 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002630 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002631}
2632
2633
Ian Rogers2c8f6532011-09-02 17:16:34 -07002634void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002635 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2636 EmitUint8(0x0F);
2637 EmitUint8(0xB1);
2638 EmitOperand(reg, address);
2639}
2640
Mark Mendell58d25fd2015-04-03 14:52:31 -04002641
2642void X86Assembler::cmpxchg8b(const Address& address) {
2643 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2644 EmitUint8(0x0F);
2645 EmitUint8(0xC7);
2646 EmitOperand(1, address);
2647}
2648
2649
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002650void X86Assembler::mfence() {
2651 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2652 EmitUint8(0x0F);
2653 EmitUint8(0xAE);
2654 EmitUint8(0xF0);
2655}
2656
Ian Rogers2c8f6532011-09-02 17:16:34 -07002657X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002658 // TODO: fs is a prefix and not an instruction
2659 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2660 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002661 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002662}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002663
Ian Rogersbefbd572014-03-06 01:13:39 -08002664X86Assembler* X86Assembler::gs() {
2665 // TODO: fs is a prefix and not an instruction
2666 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2667 EmitUint8(0x65);
2668 return this;
2669}
2670
Ian Rogers2c8f6532011-09-02 17:16:34 -07002671void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002672 int value = imm.value();
2673 if (value > 0) {
2674 if (value == 1) {
2675 incl(reg);
2676 } else if (value != 0) {
2677 addl(reg, imm);
2678 }
2679 } else if (value < 0) {
2680 value = -value;
2681 if (value == 1) {
2682 decl(reg);
2683 } else if (value != 0) {
2684 subl(reg, Immediate(value));
2685 }
2686 }
2687}
2688
2689
Roland Levillain647b9ed2014-11-27 12:06:00 +00002690void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2691 // TODO: Need to have a code constants table.
2692 pushl(Immediate(High32Bits(value)));
2693 pushl(Immediate(Low32Bits(value)));
2694 movsd(dst, Address(ESP, 0));
2695 addl(ESP, Immediate(2 * sizeof(int32_t)));
2696}
2697
2698
Ian Rogers2c8f6532011-09-02 17:16:34 -07002699void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002700 // TODO: Need to have a code constants table.
2701 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002702 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002703}
2704
2705
Ian Rogers2c8f6532011-09-02 17:16:34 -07002706void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002707 CHECK(IsPowerOfTwo(alignment));
2708 // Emit nop instruction until the real position is aligned.
2709 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2710 nop();
2711 }
2712}
2713
2714
Ian Rogers2c8f6532011-09-02 17:16:34 -07002715void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002716 int bound = buffer_.Size();
2717 CHECK(!label->IsBound()); // Labels can only be bound once.
2718 while (label->IsLinked()) {
2719 int position = label->LinkPosition();
2720 int next = buffer_.Load<int32_t>(position);
2721 buffer_.Store<int32_t>(position, bound - (position + 4));
2722 label->position_ = next;
2723 }
2724 label->BindTo(bound);
2725}
2726
2727
Mark Mendell73f455e2015-08-21 09:30:05 -04002728void X86Assembler::Bind(NearLabel* label) {
2729 int bound = buffer_.Size();
2730 CHECK(!label->IsBound()); // Labels can only be bound once.
2731 while (label->IsLinked()) {
2732 int position = label->LinkPosition();
2733 uint8_t delta = buffer_.Load<uint8_t>(position);
2734 int offset = bound - (position + 1);
2735 CHECK(IsInt<8>(offset));
2736 buffer_.Store<int8_t>(position, offset);
2737 label->position_ = delta != 0u ? label->position_ - delta : 0;
2738 }
2739 label->BindTo(bound);
2740}
2741
2742
Ian Rogers44fb0d02012-03-23 16:46:24 -07002743void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2744 CHECK_GE(reg_or_opcode, 0);
2745 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002746 const int length = operand.length_;
2747 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002748 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002749 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002750 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002751 // Emit the rest of the encoded operand.
2752 for (int i = 1; i < length; i++) {
2753 EmitUint8(operand.encoding_[i]);
2754 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002755 AssemblerFixup* fixup = operand.GetFixup();
2756 if (fixup != nullptr) {
2757 EmitFixup(fixup);
2758 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002759}
2760
2761
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002762void X86Assembler::EmitImmediate(const Immediate& imm, bool is_16_op) {
2763 if (is_16_op) {
2764 EmitUint8(imm.value() & 0xFF);
2765 EmitUint8(imm.value() >> 8);
2766 } else {
2767 EmitInt32(imm.value());
2768 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002769}
2770
2771
Ian Rogers44fb0d02012-03-23 16:46:24 -07002772void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002773 const Operand& operand,
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002774 const Immediate& immediate,
2775 bool is_16_op) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002776 CHECK_GE(reg_or_opcode, 0);
2777 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002778 if (immediate.is_int8()) {
2779 // Use sign-extended 8-bit immediate.
2780 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002781 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002782 EmitUint8(immediate.value() & 0xFF);
2783 } else if (operand.IsRegister(EAX)) {
2784 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002785 EmitUint8(0x05 + (reg_or_opcode << 3));
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002786 EmitImmediate(immediate, is_16_op);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002787 } else {
2788 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002789 EmitOperand(reg_or_opcode, operand);
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002790 EmitImmediate(immediate, is_16_op);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002791 }
2792}
2793
2794
Ian Rogers2c8f6532011-09-02 17:16:34 -07002795void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002796 if (label->IsBound()) {
2797 int offset = label->Position() - buffer_.Size();
2798 CHECK_LE(offset, 0);
2799 EmitInt32(offset - instruction_size);
2800 } else {
2801 EmitLabelLink(label);
2802 }
2803}
2804
2805
Ian Rogers2c8f6532011-09-02 17:16:34 -07002806void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002807 CHECK(!label->IsBound());
2808 int position = buffer_.Size();
2809 EmitInt32(label->position_);
2810 label->LinkTo(position);
2811}
2812
2813
Mark Mendell73f455e2015-08-21 09:30:05 -04002814void X86Assembler::EmitLabelLink(NearLabel* label) {
2815 CHECK(!label->IsBound());
2816 int position = buffer_.Size();
2817 if (label->IsLinked()) {
2818 // Save the delta in the byte that we have to play with.
2819 uint32_t delta = position - label->LinkPosition();
2820 CHECK(IsUint<8>(delta));
2821 EmitUint8(delta & 0xFF);
2822 } else {
2823 EmitUint8(0);
2824 }
2825 label->LinkTo(position);
2826}
2827
2828
Ian Rogers44fb0d02012-03-23 16:46:24 -07002829void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002830 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002831 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002832 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2833 CHECK(imm.is_int8());
2834 if (imm.value() == 1) {
2835 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002836 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002837 } else {
2838 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002839 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002840 EmitUint8(imm.value() & 0xFF);
2841 }
2842}
2843
2844
Ian Rogers44fb0d02012-03-23 16:46:24 -07002845void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002846 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002847 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002848 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2849 CHECK_EQ(shifter, ECX);
2850 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002851 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002852}
2853
Mark Mendell0616ae02015-04-17 12:49:27 -04002854void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002855 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002856 // Generate the data for the literal area.
2857 for (size_t i = 0, e = area.size(); i < e; i++) {
2858 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2859 EmitInt32(area[i]);
2860 }
2861}
2862
Mark Mendell805b3b52015-09-18 14:10:29 -04002863size_t ConstantArea::AppendInt32(int32_t v) {
2864 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002865 buffer_.push_back(v);
2866 return result;
2867}
2868
Mark Mendell805b3b52015-09-18 14:10:29 -04002869size_t ConstantArea::AddInt32(int32_t v) {
2870 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2871 if (v == buffer_[i]) {
2872 return i * elem_size_;
2873 }
2874 }
2875
2876 // Didn't match anything.
2877 return AppendInt32(v);
2878}
2879
2880size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002881 int32_t v_low = Low32Bits(v);
2882 int32_t v_high = High32Bits(v);
2883 if (buffer_.size() > 1) {
2884 // Ensure we don't pass the end of the buffer.
2885 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2886 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002887 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002888 }
2889 }
2890 }
2891
2892 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002893 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002894 buffer_.push_back(v_low);
2895 buffer_.push_back(v_high);
2896 return result;
2897}
2898
Mark Mendell805b3b52015-09-18 14:10:29 -04002899size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002900 // Treat the value as a 64-bit integer value.
2901 return AddInt64(bit_cast<int64_t, double>(v));
2902}
2903
Mark Mendell805b3b52015-09-18 14:10:29 -04002904size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002905 // Treat the value as a 32-bit integer value.
2906 return AddInt32(bit_cast<int32_t, float>(v));
2907}
2908
Ian Rogers2c8f6532011-09-02 17:16:34 -07002909} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002910} // namespace art