blob: c2ce03b1f297f34dfe4af2c590c97d547f77bc0e [file] [log] [blame]
Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
David Sehr1ce2b3b2018-04-05 11:02:03 -070020#include "base/memory_region.h"
Ian Rogers166db042013-07-26 12:05:57 -070021#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Aart Bikcaa31e72017-09-14 17:08:50 -070035std::ostream& operator<<(std::ostream& os, const Address& addr) {
36 switch (addr.mod()) {
37 case 0:
Aart Bikf7754e82017-09-20 10:33:06 -070038 if (addr.rm() != ESP || addr.index() == ESP) {
39 return os << "(%" << addr.rm() << ")";
40 } else if (addr.base() == EBP) {
41 return os << static_cast<int>(addr.disp32()) << "(,%" << addr.index()
42 << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070043 }
Aart Bikf7754e82017-09-20 10:33:06 -070044 return os << "(%" << addr.base() << ",%" << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070045 case 1:
Aart Bikf7754e82017-09-20 10:33:06 -070046 if (addr.rm() != ESP || addr.index() == ESP) {
47 return os << static_cast<int>(addr.disp8()) << "(%" << addr.rm() << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070048 }
Aart Bikf7754e82017-09-20 10:33:06 -070049 return os << static_cast<int>(addr.disp8()) << "(%" << addr.base() << ",%"
50 << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070051 case 2:
Aart Bikf7754e82017-09-20 10:33:06 -070052 if (addr.rm() != ESP || addr.index() == ESP) {
53 return os << static_cast<int>(addr.disp32()) << "(%" << addr.rm() << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070054 }
Aart Bikf7754e82017-09-20 10:33:06 -070055 return os << static_cast<int>(addr.disp32()) << "(%" << addr.base() << ",%"
56 << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070057 default:
58 return os << "<address?>";
59 }
60}
61
Ian Rogers2c8f6532011-09-02 17:16:34 -070062void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070063 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
64 EmitUint8(0xFF);
65 EmitRegisterOperand(2, reg);
66}
67
68
Ian Rogers2c8f6532011-09-02 17:16:34 -070069void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070070 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71 EmitUint8(0xFF);
72 EmitOperand(2, address);
73}
74
75
Ian Rogers2c8f6532011-09-02 17:16:34 -070076void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070077 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
78 EmitUint8(0xE8);
79 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000080 // Offset by one because we already have emitted the opcode.
81 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082}
83
84
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000085void X86Assembler::call(const ExternalLabel& label) {
86 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
87 intptr_t call_start = buffer_.GetPosition();
88 EmitUint8(0xE8);
89 EmitInt32(label.address());
90 static const intptr_t kCallExternalLabelSize = 5;
91 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
92}
93
94
Ian Rogers2c8f6532011-09-02 17:16:34 -070095void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
97 EmitUint8(0x50 + reg);
98}
99
100
Ian Rogers2c8f6532011-09-02 17:16:34 -0700101void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700102 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
103 EmitUint8(0xFF);
104 EmitOperand(6, address);
105}
106
107
Ian Rogers2c8f6532011-09-02 17:16:34 -0700108void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700109 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -0700110 if (imm.is_int8()) {
111 EmitUint8(0x6A);
112 EmitUint8(imm.value() & 0xFF);
113 } else {
114 EmitUint8(0x68);
115 EmitImmediate(imm);
116 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x58 + reg);
123}
124
125
Ian Rogers2c8f6532011-09-02 17:16:34 -0700126void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700127 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
128 EmitUint8(0x8F);
129 EmitOperand(0, address);
130}
131
132
Ian Rogers2c8f6532011-09-02 17:16:34 -0700133void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700134 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
135 EmitUint8(0xB8 + dst);
136 EmitImmediate(imm);
137}
138
139
Ian Rogers2c8f6532011-09-02 17:16:34 -0700140void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700141 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
142 EmitUint8(0x89);
143 EmitRegisterOperand(src, dst);
144}
145
146
Ian Rogers2c8f6532011-09-02 17:16:34 -0700147void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
149 EmitUint8(0x8B);
150 EmitOperand(dst, src);
151}
152
153
Ian Rogers2c8f6532011-09-02 17:16:34 -0700154void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700155 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
156 EmitUint8(0x89);
157 EmitOperand(src, dst);
158}
159
160
Ian Rogers2c8f6532011-09-02 17:16:34 -0700161void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0xC7);
164 EmitOperand(0, dst);
165 EmitImmediate(imm);
166}
167
Ian Rogersbdb03912011-09-14 00:55:44 -0700168void X86Assembler::movl(const Address& dst, Label* lbl) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0xC7);
171 EmitOperand(0, dst);
172 EmitLabel(lbl, dst.length_ + 5);
173}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700174
Mark Mendell7a08fb52015-07-15 14:09:35 -0400175void X86Assembler::movntl(const Address& dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xC3);
179 EmitOperand(src, dst);
180}
181
Mark Mendell09ed1a32015-03-25 08:30:06 -0400182void X86Assembler::bswapl(Register dst) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xC8 + dst);
186}
187
Mark Mendellbcee0922015-09-15 21:45:01 -0400188void X86Assembler::bsfl(Register dst, Register src) {
189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
190 EmitUint8(0x0F);
191 EmitUint8(0xBC);
192 EmitRegisterOperand(dst, src);
193}
194
195void X86Assembler::bsfl(Register dst, const Address& src) {
196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
197 EmitUint8(0x0F);
198 EmitUint8(0xBC);
199 EmitOperand(dst, src);
200}
201
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400202void X86Assembler::bsrl(Register dst, Register src) {
203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
204 EmitUint8(0x0F);
205 EmitUint8(0xBD);
206 EmitRegisterOperand(dst, src);
207}
208
209void X86Assembler::bsrl(Register dst, const Address& src) {
210 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
211 EmitUint8(0x0F);
212 EmitUint8(0xBD);
213 EmitOperand(dst, src);
214}
215
Aart Bikc39dac12016-01-21 08:59:48 -0800216void X86Assembler::popcntl(Register dst, Register src) {
217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
218 EmitUint8(0xF3);
219 EmitUint8(0x0F);
220 EmitUint8(0xB8);
221 EmitRegisterOperand(dst, src);
222}
223
224void X86Assembler::popcntl(Register dst, const Address& src) {
225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
226 EmitUint8(0xF3);
227 EmitUint8(0x0F);
228 EmitUint8(0xB8);
229 EmitOperand(dst, src);
230}
231
Ian Rogers2c8f6532011-09-02 17:16:34 -0700232void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700233 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
234 EmitUint8(0x0F);
235 EmitUint8(0xB6);
236 EmitRegisterOperand(dst, src);
237}
238
239
Ian Rogers2c8f6532011-09-02 17:16:34 -0700240void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700241 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
242 EmitUint8(0x0F);
243 EmitUint8(0xB6);
244 EmitOperand(dst, src);
245}
246
247
Ian Rogers2c8f6532011-09-02 17:16:34 -0700248void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700249 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
250 EmitUint8(0x0F);
251 EmitUint8(0xBE);
252 EmitRegisterOperand(dst, src);
253}
254
255
Ian Rogers2c8f6532011-09-02 17:16:34 -0700256void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700257 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
258 EmitUint8(0x0F);
259 EmitUint8(0xBE);
260 EmitOperand(dst, src);
261}
262
263
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700264void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700265 LOG(FATAL) << "Use movzxb or movsxb instead.";
266}
267
268
Ian Rogers2c8f6532011-09-02 17:16:34 -0700269void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700270 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
271 EmitUint8(0x88);
272 EmitOperand(src, dst);
273}
274
275
Ian Rogers2c8f6532011-09-02 17:16:34 -0700276void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700277 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
278 EmitUint8(0xC6);
279 EmitOperand(EAX, dst);
280 CHECK(imm.is_int8());
281 EmitUint8(imm.value() & 0xFF);
282}
283
284
Ian Rogers2c8f6532011-09-02 17:16:34 -0700285void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700286 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
287 EmitUint8(0x0F);
288 EmitUint8(0xB7);
289 EmitRegisterOperand(dst, src);
290}
291
292
Ian Rogers2c8f6532011-09-02 17:16:34 -0700293void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700294 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
295 EmitUint8(0x0F);
296 EmitUint8(0xB7);
297 EmitOperand(dst, src);
298}
299
300
Ian Rogers2c8f6532011-09-02 17:16:34 -0700301void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700302 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
303 EmitUint8(0x0F);
304 EmitUint8(0xBF);
305 EmitRegisterOperand(dst, src);
306}
307
308
Ian Rogers2c8f6532011-09-02 17:16:34 -0700309void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700310 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
311 EmitUint8(0x0F);
312 EmitUint8(0xBF);
313 EmitOperand(dst, src);
314}
315
316
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700317void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700318 LOG(FATAL) << "Use movzxw or movsxw instead.";
319}
320
321
Ian Rogers2c8f6532011-09-02 17:16:34 -0700322void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700323 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
324 EmitOperandSizeOverride();
325 EmitUint8(0x89);
326 EmitOperand(src, dst);
327}
328
329
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100330void X86Assembler::movw(const Address& dst, const Immediate& imm) {
331 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
332 EmitOperandSizeOverride();
333 EmitUint8(0xC7);
334 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100335 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100336 EmitUint8(imm.value() & 0xFF);
337 EmitUint8(imm.value() >> 8);
338}
339
340
Ian Rogers2c8f6532011-09-02 17:16:34 -0700341void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
343 EmitUint8(0x8D);
344 EmitOperand(dst, src);
345}
346
347
Ian Rogers2c8f6532011-09-02 17:16:34 -0700348void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700349 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
350 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700351 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700352 EmitRegisterOperand(dst, src);
353}
354
355
Mark Mendellabdac472016-02-12 13:49:03 -0500356void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
357 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
358 EmitUint8(0x0F);
359 EmitUint8(0x40 + condition);
360 EmitOperand(dst, src);
361}
362
363
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000364void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700365 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
366 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700367 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000368 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700369}
370
371
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100372void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
373 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
374 EmitUint8(0x0F);
375 EmitUint8(0x28);
376 EmitXmmRegisterOperand(dst, src);
377}
378
379
Aart Bikc7782262017-01-13 16:20:08 -0800380void X86Assembler::movaps(XmmRegister dst, const Address& src) {
381 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
382 EmitUint8(0x0F);
383 EmitUint8(0x28);
384 EmitOperand(dst, src);
385}
386
387
388void X86Assembler::movups(XmmRegister dst, const Address& src) {
389 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
390 EmitUint8(0x0F);
391 EmitUint8(0x10);
392 EmitOperand(dst, src);
393}
394
395
396void X86Assembler::movaps(const Address& dst, XmmRegister src) {
397 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
398 EmitUint8(0x0F);
399 EmitUint8(0x29);
400 EmitOperand(src, dst);
401}
402
403
404void X86Assembler::movups(const Address& dst, XmmRegister src) {
405 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0xF3);
415 EmitUint8(0x0F);
416 EmitUint8(0x10);
417 EmitOperand(dst, src);
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0xF3);
424 EmitUint8(0x0F);
425 EmitUint8(0x11);
426 EmitOperand(src, dst);
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x11);
435 EmitXmmRegisterOperand(src, dst);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0x66);
442 EmitUint8(0x0F);
443 EmitUint8(0x6E);
444 EmitOperand(dst, Operand(src));
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0x66);
451 EmitUint8(0x0F);
452 EmitUint8(0x7E);
453 EmitOperand(src, Operand(dst));
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x58);
462 EmitXmmRegisterOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x58);
471 EmitOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x5C);
480 EmitXmmRegisterOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5C);
489 EmitOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x59);
498 EmitXmmRegisterOperand(dst, src);
499}
500
501
Ian Rogers2c8f6532011-09-02 17:16:34 -0700502void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0xF3);
505 EmitUint8(0x0F);
506 EmitUint8(0x59);
507 EmitOperand(dst, src);
508}
509
510
Ian Rogers2c8f6532011-09-02 17:16:34 -0700511void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700512 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
513 EmitUint8(0xF3);
514 EmitUint8(0x0F);
515 EmitUint8(0x5E);
516 EmitXmmRegisterOperand(dst, src);
517}
518
519
Ian Rogers2c8f6532011-09-02 17:16:34 -0700520void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700521 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
522 EmitUint8(0xF3);
523 EmitUint8(0x0F);
524 EmitUint8(0x5E);
525 EmitOperand(dst, src);
526}
527
Gupta Kumar, Sanjiv61908882018-06-29 13:06:35 +0530528void X86Assembler::vfmadd231ps(XmmRegister acc, XmmRegister mul_left, XmmRegister mul_right) {
529 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
530 uint8_t byte_zero = EmitVexByteZero(false /*is_two_byte*/);
531 uint8_t byte_one = EmitVexByte1(false, false, false, 2);
532 uint8_t byte_two = EmitVexByte2(false, 128, X86ManagedRegister::FromXmmRegister(mul_left), 1);
533 EmitUint8(byte_zero);
534 EmitUint8(byte_one);
535 EmitUint8(byte_two);
536 // Opcode field.
537 EmitUint8(0xB8);
538 EmitXmmRegisterOperand(acc, mul_right);
539}
540
541void X86Assembler::vfmsub231ps(XmmRegister acc, XmmRegister mul_left, XmmRegister mul_right) {
542 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
543 uint8_t byte_zero = EmitVexByteZero(false /*is_two_byte*/);
544 uint8_t byte_one = EmitVexByte1(false, false, false, 2);
545 uint8_t byte_two = EmitVexByte2(false, 128, X86ManagedRegister::FromXmmRegister(mul_left), 1);
546 EmitUint8(byte_zero);
547 EmitUint8(byte_one);
548 EmitUint8(byte_two);
549 // Opcode field.
550 EmitUint8(0xBA);
551 EmitXmmRegisterOperand(acc, mul_right);
552}
553
554void X86Assembler::vfmadd231pd(XmmRegister acc, XmmRegister mul_left, XmmRegister mul_right) {
555 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
556 uint8_t byte_zero = EmitVexByteZero(false /*is_two_byte*/);
557 uint8_t byte_one = EmitVexByte1(false, false, false, 2);
558 uint8_t byte_two = EmitVexByte2(true, 128, X86ManagedRegister::FromXmmRegister(mul_left), 1);
559 EmitUint8(byte_zero);
560 EmitUint8(byte_one);
561 EmitUint8(byte_two);
562 // Opcode field.
563 EmitUint8(0xB8);
564 EmitXmmRegisterOperand(acc, mul_right);
565}
566
567void X86Assembler::vfmsub231pd(XmmRegister acc, XmmRegister mul_left, XmmRegister mul_right) {
568 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
569 uint8_t byte_zero = EmitVexByteZero(false /*is_two_byte*/);
570 uint8_t byte_one = EmitVexByte1(false, false, false, 2);
571 uint8_t byte_two = EmitVexByte2(true, 128, X86ManagedRegister::FromXmmRegister(mul_left), 1);
572 EmitUint8(byte_zero);
573 EmitUint8(byte_one);
574 EmitUint8(byte_two);
575 // Opcode field.
576 EmitUint8(0xBA);
577 EmitXmmRegisterOperand(acc, mul_right);
578}
579
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580
Aart Bikc7782262017-01-13 16:20:08 -0800581void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
582 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
583 EmitUint8(0x0F);
584 EmitUint8(0x58);
585 EmitXmmRegisterOperand(dst, src);
586}
587
588
589void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
590 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
591 EmitUint8(0x0F);
592 EmitUint8(0x5C);
593 EmitXmmRegisterOperand(dst, src);
594}
595
596
597void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
598 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
599 EmitUint8(0x0F);
600 EmitUint8(0x59);
601 EmitXmmRegisterOperand(dst, src);
602}
603
604
605void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
606 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
607 EmitUint8(0x0F);
608 EmitUint8(0x5E);
609 EmitXmmRegisterOperand(dst, src);
610}
611
612
613void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
614 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
615 EmitUint8(0x66);
616 EmitUint8(0x0F);
617 EmitUint8(0x28);
618 EmitXmmRegisterOperand(dst, src);
619}
620
621
622void X86Assembler::movapd(XmmRegister dst, const Address& src) {
623 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
624 EmitUint8(0x66);
625 EmitUint8(0x0F);
626 EmitUint8(0x28);
627 EmitOperand(dst, src);
628}
629
630
631void X86Assembler::movupd(XmmRegister dst, const Address& src) {
632 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
633 EmitUint8(0x66);
634 EmitUint8(0x0F);
635 EmitUint8(0x10);
636 EmitOperand(dst, src);
637}
638
639
640void X86Assembler::movapd(const Address& dst, XmmRegister src) {
641 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
642 EmitUint8(0x66);
643 EmitUint8(0x0F);
644 EmitUint8(0x29);
645 EmitOperand(src, dst);
646}
647
648
649void X86Assembler::movupd(const Address& dst, XmmRegister src) {
650 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
651 EmitUint8(0x66);
652 EmitUint8(0x0F);
653 EmitUint8(0x11);
654 EmitOperand(src, dst);
655}
656
657
Ian Rogers2c8f6532011-09-02 17:16:34 -0700658void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700659 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
660 EmitUint8(0xD9);
661 EmitOperand(0, src);
662}
663
664
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500665void X86Assembler::fsts(const Address& dst) {
666 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
667 EmitUint8(0xD9);
668 EmitOperand(2, dst);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xD9);
675 EmitOperand(3, dst);
676}
677
678
Ian Rogers2c8f6532011-09-02 17:16:34 -0700679void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700680 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
681 EmitUint8(0xF2);
682 EmitUint8(0x0F);
683 EmitUint8(0x10);
684 EmitOperand(dst, src);
685}
686
687
Ian Rogers2c8f6532011-09-02 17:16:34 -0700688void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700689 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
690 EmitUint8(0xF2);
691 EmitUint8(0x0F);
692 EmitUint8(0x11);
693 EmitOperand(src, dst);
694}
695
696
Ian Rogers2c8f6532011-09-02 17:16:34 -0700697void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700698 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
699 EmitUint8(0xF2);
700 EmitUint8(0x0F);
701 EmitUint8(0x11);
702 EmitXmmRegisterOperand(src, dst);
703}
704
705
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000706void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
707 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
708 EmitUint8(0x66);
709 EmitUint8(0x0F);
710 EmitUint8(0x16);
711 EmitOperand(dst, src);
712}
713
714
715void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
716 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
717 EmitUint8(0x66);
718 EmitUint8(0x0F);
719 EmitUint8(0x17);
720 EmitOperand(src, dst);
721}
722
723
Ian Rogers2c8f6532011-09-02 17:16:34 -0700724void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700725 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
726 EmitUint8(0xF2);
727 EmitUint8(0x0F);
728 EmitUint8(0x58);
729 EmitXmmRegisterOperand(dst, src);
730}
731
732
Ian Rogers2c8f6532011-09-02 17:16:34 -0700733void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700734 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
735 EmitUint8(0xF2);
736 EmitUint8(0x0F);
737 EmitUint8(0x58);
738 EmitOperand(dst, src);
739}
740
741
Ian Rogers2c8f6532011-09-02 17:16:34 -0700742void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700743 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
744 EmitUint8(0xF2);
745 EmitUint8(0x0F);
746 EmitUint8(0x5C);
747 EmitXmmRegisterOperand(dst, src);
748}
749
750
Ian Rogers2c8f6532011-09-02 17:16:34 -0700751void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700752 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
753 EmitUint8(0xF2);
754 EmitUint8(0x0F);
755 EmitUint8(0x5C);
756 EmitOperand(dst, src);
757}
758
759
Ian Rogers2c8f6532011-09-02 17:16:34 -0700760void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700761 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
762 EmitUint8(0xF2);
763 EmitUint8(0x0F);
764 EmitUint8(0x59);
765 EmitXmmRegisterOperand(dst, src);
766}
767
768
Ian Rogers2c8f6532011-09-02 17:16:34 -0700769void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700770 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
771 EmitUint8(0xF2);
772 EmitUint8(0x0F);
773 EmitUint8(0x59);
774 EmitOperand(dst, src);
775}
776
777
Ian Rogers2c8f6532011-09-02 17:16:34 -0700778void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700779 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
780 EmitUint8(0xF2);
781 EmitUint8(0x0F);
782 EmitUint8(0x5E);
783 EmitXmmRegisterOperand(dst, src);
784}
785
786
Ian Rogers2c8f6532011-09-02 17:16:34 -0700787void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700788 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
789 EmitUint8(0xF2);
790 EmitUint8(0x0F);
791 EmitUint8(0x5E);
792 EmitOperand(dst, src);
793}
794
795
Aart Bikc7782262017-01-13 16:20:08 -0800796void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
797 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
798 EmitUint8(0x66);
799 EmitUint8(0x0F);
800 EmitUint8(0x58);
801 EmitXmmRegisterOperand(dst, src);
802}
803
804
805void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
806 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
807 EmitUint8(0x66);
808 EmitUint8(0x0F);
809 EmitUint8(0x5C);
810 EmitXmmRegisterOperand(dst, src);
811}
812
813
814void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
815 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
816 EmitUint8(0x66);
817 EmitUint8(0x0F);
818 EmitUint8(0x59);
819 EmitXmmRegisterOperand(dst, src);
820}
821
822
823void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
824 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
825 EmitUint8(0x66);
826 EmitUint8(0x0F);
827 EmitUint8(0x5E);
828 EmitXmmRegisterOperand(dst, src);
829}
830
831
Aart Bik68555e92017-02-13 14:28:45 -0800832void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
833 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
834 EmitUint8(0x66);
835 EmitUint8(0x0F);
836 EmitUint8(0x6F);
837 EmitXmmRegisterOperand(dst, src);
838}
839
840
841void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
842 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
843 EmitUint8(0x66);
844 EmitUint8(0x0F);
845 EmitUint8(0x6F);
846 EmitOperand(dst, src);
847}
848
849
850void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
851 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
852 EmitUint8(0xF3);
853 EmitUint8(0x0F);
854 EmitUint8(0x6F);
855 EmitOperand(dst, src);
856}
857
858
859void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
860 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
861 EmitUint8(0x66);
862 EmitUint8(0x0F);
863 EmitUint8(0x7F);
864 EmitOperand(src, dst);
865}
866
867
868void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
869 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
870 EmitUint8(0xF3);
871 EmitUint8(0x0F);
872 EmitUint8(0x7F);
873 EmitOperand(src, dst);
874}
875
876
Aart Bike69d7a92017-02-17 11:48:23 -0800877void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
878 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
879 EmitUint8(0x66);
880 EmitUint8(0x0F);
881 EmitUint8(0xFC);
882 EmitXmmRegisterOperand(dst, src);
883}
884
885
886void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
887 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
888 EmitUint8(0x66);
889 EmitUint8(0x0F);
890 EmitUint8(0xF8);
891 EmitXmmRegisterOperand(dst, src);
892}
893
894
895void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
896 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
897 EmitUint8(0x66);
898 EmitUint8(0x0F);
899 EmitUint8(0xFD);
900 EmitXmmRegisterOperand(dst, src);
901}
902
903
904void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
905 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
906 EmitUint8(0x66);
907 EmitUint8(0x0F);
908 EmitUint8(0xF9);
909 EmitXmmRegisterOperand(dst, src);
910}
911
912
913void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
914 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
915 EmitUint8(0x66);
916 EmitUint8(0x0F);
917 EmitUint8(0xD5);
918 EmitXmmRegisterOperand(dst, src);
919}
920
921
Aart Bik68555e92017-02-13 14:28:45 -0800922void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
923 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
924 EmitUint8(0x66);
925 EmitUint8(0x0F);
926 EmitUint8(0xFE);
927 EmitXmmRegisterOperand(dst, src);
928}
929
930
931void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
932 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
933 EmitUint8(0x66);
934 EmitUint8(0x0F);
935 EmitUint8(0xFA);
936 EmitXmmRegisterOperand(dst, src);
937}
938
939
940void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
941 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
942 EmitUint8(0x66);
943 EmitUint8(0x0F);
944 EmitUint8(0x38);
945 EmitUint8(0x40);
946 EmitXmmRegisterOperand(dst, src);
947}
948
949
Aart Bike69d7a92017-02-17 11:48:23 -0800950void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
951 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
952 EmitUint8(0x66);
953 EmitUint8(0x0F);
954 EmitUint8(0xD4);
955 EmitXmmRegisterOperand(dst, src);
956}
957
958
959void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
960 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
961 EmitUint8(0x66);
962 EmitUint8(0x0F);
963 EmitUint8(0xFB);
964 EmitXmmRegisterOperand(dst, src);
965}
966
967
Aart Bik4ca17352018-03-07 15:47:39 -0800968void X86Assembler::paddusb(XmmRegister dst, XmmRegister src) {
969 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
970 EmitUint8(0x66);
971 EmitUint8(0x0F);
972 EmitUint8(0xDC);
973 EmitXmmRegisterOperand(dst, src);
974}
975
976
977void X86Assembler::paddsb(XmmRegister dst, XmmRegister src) {
978 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
979 EmitUint8(0x66);
980 EmitUint8(0x0F);
981 EmitUint8(0xEC);
982 EmitXmmRegisterOperand(dst, src);
983}
984
985
986void X86Assembler::paddusw(XmmRegister dst, XmmRegister src) {
987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
988 EmitUint8(0x66);
989 EmitUint8(0x0F);
990 EmitUint8(0xDD);
991 EmitXmmRegisterOperand(dst, src);
992}
993
994
995void X86Assembler::paddsw(XmmRegister dst, XmmRegister src) {
996 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
997 EmitUint8(0x66);
998 EmitUint8(0x0F);
999 EmitUint8(0xED);
1000 EmitXmmRegisterOperand(dst, src);
1001}
1002
1003
1004void X86Assembler::psubusb(XmmRegister dst, XmmRegister src) {
1005 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1006 EmitUint8(0x66);
1007 EmitUint8(0x0F);
1008 EmitUint8(0xD8);
1009 EmitXmmRegisterOperand(dst, src);
1010}
1011
1012
1013void X86Assembler::psubsb(XmmRegister dst, XmmRegister src) {
1014 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1015 EmitUint8(0x66);
1016 EmitUint8(0x0F);
1017 EmitUint8(0xE8);
1018 EmitXmmRegisterOperand(dst, src);
1019}
1020
1021
1022void X86Assembler::psubusw(XmmRegister dst, XmmRegister src) {
1023 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1024 EmitUint8(0x66);
1025 EmitUint8(0x0F);
1026 EmitUint8(0xD9);
1027 EmitXmmRegisterOperand(dst, src);
1028}
1029
1030
1031void X86Assembler::psubsw(XmmRegister dst, XmmRegister src) {
1032 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1033 EmitUint8(0x66);
1034 EmitUint8(0x0F);
1035 EmitUint8(0xE9);
1036 EmitXmmRegisterOperand(dst, src);
1037}
1038
1039
Ian Rogers2c8f6532011-09-02 17:16:34 -07001040void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001041 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1042 EmitUint8(0xF3);
1043 EmitUint8(0x0F);
1044 EmitUint8(0x2A);
1045 EmitOperand(dst, Operand(src));
1046}
1047
1048
Ian Rogers2c8f6532011-09-02 17:16:34 -07001049void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1051 EmitUint8(0xF2);
1052 EmitUint8(0x0F);
1053 EmitUint8(0x2A);
1054 EmitOperand(dst, Operand(src));
1055}
1056
1057
Ian Rogers2c8f6532011-09-02 17:16:34 -07001058void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001059 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1060 EmitUint8(0xF3);
1061 EmitUint8(0x0F);
1062 EmitUint8(0x2D);
1063 EmitXmmRegisterOperand(dst, src);
1064}
1065
1066
Ian Rogers2c8f6532011-09-02 17:16:34 -07001067void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001068 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1069 EmitUint8(0xF3);
1070 EmitUint8(0x0F);
1071 EmitUint8(0x5A);
1072 EmitXmmRegisterOperand(dst, src);
1073}
1074
1075
Ian Rogers2c8f6532011-09-02 17:16:34 -07001076void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001077 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1078 EmitUint8(0xF2);
1079 EmitUint8(0x0F);
1080 EmitUint8(0x2D);
1081 EmitXmmRegisterOperand(dst, src);
1082}
1083
1084
Ian Rogers2c8f6532011-09-02 17:16:34 -07001085void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001086 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1087 EmitUint8(0xF3);
1088 EmitUint8(0x0F);
1089 EmitUint8(0x2C);
1090 EmitXmmRegisterOperand(dst, src);
1091}
1092
1093
Ian Rogers2c8f6532011-09-02 17:16:34 -07001094void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001095 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1096 EmitUint8(0xF2);
1097 EmitUint8(0x0F);
1098 EmitUint8(0x2C);
1099 EmitXmmRegisterOperand(dst, src);
1100}
1101
1102
Ian Rogers2c8f6532011-09-02 17:16:34 -07001103void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001104 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1105 EmitUint8(0xF2);
1106 EmitUint8(0x0F);
1107 EmitUint8(0x5A);
1108 EmitXmmRegisterOperand(dst, src);
1109}
1110
1111
Aart Bik3ae3b592017-02-24 14:09:15 -08001112void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
1113 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1114 EmitUint8(0x0F);
1115 EmitUint8(0x5B);
1116 EmitXmmRegisterOperand(dst, src);
1117}
1118
1119
Ian Rogers2c8f6532011-09-02 17:16:34 -07001120void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1122 EmitUint8(0xF3);
1123 EmitUint8(0x0F);
1124 EmitUint8(0xE6);
1125 EmitXmmRegisterOperand(dst, src);
1126}
1127
1128
Ian Rogers2c8f6532011-09-02 17:16:34 -07001129void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131 EmitUint8(0x0F);
1132 EmitUint8(0x2F);
1133 EmitXmmRegisterOperand(a, b);
1134}
1135
1136
Aart Bik18ba1212016-08-01 14:11:20 -07001137void X86Assembler::comiss(XmmRegister a, const Address& b) {
1138 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1139 EmitUint8(0x0F);
1140 EmitUint8(0x2F);
1141 EmitOperand(a, b);
1142}
1143
1144
Ian Rogers2c8f6532011-09-02 17:16:34 -07001145void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001146 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1147 EmitUint8(0x66);
1148 EmitUint8(0x0F);
1149 EmitUint8(0x2F);
1150 EmitXmmRegisterOperand(a, b);
1151}
1152
1153
Aart Bik18ba1212016-08-01 14:11:20 -07001154void X86Assembler::comisd(XmmRegister a, const Address& b) {
1155 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1156 EmitUint8(0x66);
1157 EmitUint8(0x0F);
1158 EmitUint8(0x2F);
1159 EmitOperand(a, b);
1160}
1161
1162
Calin Juravleddb7df22014-11-25 20:56:51 +00001163void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1164 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1165 EmitUint8(0x0F);
1166 EmitUint8(0x2E);
1167 EmitXmmRegisterOperand(a, b);
1168}
1169
1170
Mark Mendell9f51f262015-10-30 09:21:37 -04001171void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1172 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1173 EmitUint8(0x0F);
1174 EmitUint8(0x2E);
1175 EmitOperand(a, b);
1176}
1177
1178
Calin Juravleddb7df22014-11-25 20:56:51 +00001179void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1180 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1181 EmitUint8(0x66);
1182 EmitUint8(0x0F);
1183 EmitUint8(0x2E);
1184 EmitXmmRegisterOperand(a, b);
1185}
1186
1187
Mark Mendell9f51f262015-10-30 09:21:37 -04001188void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1190 EmitUint8(0x66);
1191 EmitUint8(0x0F);
1192 EmitUint8(0x2E);
1193 EmitOperand(a, b);
1194}
1195
1196
Mark Mendellfb8d2792015-03-31 22:16:59 -04001197void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1199 EmitUint8(0x66);
1200 EmitUint8(0x0F);
1201 EmitUint8(0x3A);
1202 EmitUint8(0x0B);
1203 EmitXmmRegisterOperand(dst, src);
1204 EmitUint8(imm.value());
1205}
1206
1207
1208void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1209 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1210 EmitUint8(0x66);
1211 EmitUint8(0x0F);
1212 EmitUint8(0x3A);
1213 EmitUint8(0x0A);
1214 EmitXmmRegisterOperand(dst, src);
1215 EmitUint8(imm.value());
1216}
1217
1218
Ian Rogers2c8f6532011-09-02 17:16:34 -07001219void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001220 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1221 EmitUint8(0xF2);
1222 EmitUint8(0x0F);
1223 EmitUint8(0x51);
1224 EmitXmmRegisterOperand(dst, src);
1225}
1226
1227
Ian Rogers2c8f6532011-09-02 17:16:34 -07001228void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001229 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1230 EmitUint8(0xF3);
1231 EmitUint8(0x0F);
1232 EmitUint8(0x51);
1233 EmitXmmRegisterOperand(dst, src);
1234}
1235
1236
Ian Rogers2c8f6532011-09-02 17:16:34 -07001237void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001238 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1239 EmitUint8(0x66);
1240 EmitUint8(0x0F);
1241 EmitUint8(0x57);
1242 EmitOperand(dst, src);
1243}
1244
1245
Ian Rogers2c8f6532011-09-02 17:16:34 -07001246void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001247 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1248 EmitUint8(0x66);
1249 EmitUint8(0x0F);
1250 EmitUint8(0x57);
1251 EmitXmmRegisterOperand(dst, src);
1252}
1253
1254
Aart Bik68555e92017-02-13 14:28:45 -08001255void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001256 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1257 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001258 EmitUint8(0x57);
1259 EmitOperand(dst, src);
1260}
1261
1262
1263void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1264 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1265 EmitUint8(0x0F);
1266 EmitUint8(0x57);
1267 EmitXmmRegisterOperand(dst, src);
1268}
1269
1270
1271void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1272 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1273 EmitUint8(0x66);
1274 EmitUint8(0x0F);
1275 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001276 EmitXmmRegisterOperand(dst, src);
1277}
1278
1279
1280void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1281 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1282 EmitUint8(0x66);
1283 EmitUint8(0x0F);
1284 EmitUint8(0x54);
1285 EmitXmmRegisterOperand(dst, src);
1286}
1287
1288
Aart Bik68555e92017-02-13 14:28:45 -08001289void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001290 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1291 EmitUint8(0x66);
1292 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001293 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001294 EmitOperand(dst, src);
1295}
1296
1297
Aart Bik68555e92017-02-13 14:28:45 -08001298void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001299 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1300 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001301 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001302 EmitXmmRegisterOperand(dst, src);
1303}
1304
1305
Mark Mendell09ed1a32015-03-25 08:30:06 -04001306void X86Assembler::andps(XmmRegister dst, const Address& src) {
1307 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1308 EmitUint8(0x0F);
1309 EmitUint8(0x54);
1310 EmitOperand(dst, src);
1311}
1312
1313
Aart Bik68555e92017-02-13 14:28:45 -08001314void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1316 EmitUint8(0x66);
1317 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001318 EmitUint8(0xDB);
1319 EmitXmmRegisterOperand(dst, src);
1320}
1321
1322
Aart Bik21c580b2017-03-13 11:52:07 -07001323void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
1324 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1325 EmitUint8(0x66);
1326 EmitUint8(0x0F);
1327 EmitUint8(0x55);
1328 EmitXmmRegisterOperand(dst, src);
1329}
1330
1331
1332void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
1333 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1334 EmitUint8(0x0F);
1335 EmitUint8(0x55);
1336 EmitXmmRegisterOperand(dst, src);
1337}
1338
1339
1340void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
1341 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1342 EmitUint8(0x66);
1343 EmitUint8(0x0F);
1344 EmitUint8(0xDF);
1345 EmitXmmRegisterOperand(dst, src);
1346}
1347
1348
Aart Bik68555e92017-02-13 14:28:45 -08001349void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1350 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1351 EmitUint8(0x66);
1352 EmitUint8(0x0F);
1353 EmitUint8(0x56);
1354 EmitXmmRegisterOperand(dst, src);
1355}
1356
1357
1358void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1359 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1360 EmitUint8(0x0F);
1361 EmitUint8(0x56);
1362 EmitXmmRegisterOperand(dst, src);
1363}
1364
1365
1366void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1367 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1368 EmitUint8(0x66);
1369 EmitUint8(0x0F);
1370 EmitUint8(0xEB);
1371 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001372}
1373
1374
Aart Bik67d3fd72017-03-31 15:11:53 -07001375void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
1376 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1377 EmitUint8(0x66);
1378 EmitUint8(0x0F);
1379 EmitUint8(0xE0);
1380 EmitXmmRegisterOperand(dst, src);
1381}
1382
1383
1384void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
1385 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1386 EmitUint8(0x66);
1387 EmitUint8(0x0F);
1388 EmitUint8(0xE3);
1389 EmitXmmRegisterOperand(dst, src);
1390}
1391
Aart Bik6005a872017-07-24 13:33:39 -07001392
1393void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
1394 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1395 EmitUint8(0x66);
1396 EmitUint8(0x0F);
1397 EmitUint8(0xF6);
1398 EmitXmmRegisterOperand(dst, src);
1399}
1400
1401
1402void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
1403 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1404 EmitUint8(0x66);
1405 EmitUint8(0x0F);
1406 EmitUint8(0xF5);
1407 EmitXmmRegisterOperand(dst, src);
1408}
1409
1410
1411void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
1412 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1413 EmitUint8(0x66);
1414 EmitUint8(0x0F);
1415 EmitUint8(0x38);
1416 EmitUint8(0x01);
1417 EmitXmmRegisterOperand(dst, src);
1418}
1419
1420
1421void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
1422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1423 EmitUint8(0x66);
1424 EmitUint8(0x0F);
1425 EmitUint8(0x38);
1426 EmitUint8(0x02);
1427 EmitXmmRegisterOperand(dst, src);
1428}
1429
1430
1431void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
1432 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1433 EmitUint8(0xF2);
1434 EmitUint8(0x0F);
1435 EmitUint8(0x7C);
1436 EmitXmmRegisterOperand(dst, src);
1437}
1438
1439
1440void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
1441 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1442 EmitUint8(0x66);
1443 EmitUint8(0x0F);
1444 EmitUint8(0x7C);
1445 EmitXmmRegisterOperand(dst, src);
1446}
1447
1448
1449void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
1450 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1451 EmitUint8(0x66);
1452 EmitUint8(0x0F);
1453 EmitUint8(0x38);
1454 EmitUint8(0x05);
1455 EmitXmmRegisterOperand(dst, src);
1456}
1457
1458
1459void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
1460 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1461 EmitUint8(0x66);
1462 EmitUint8(0x0F);
1463 EmitUint8(0x38);
1464 EmitUint8(0x06);
1465 EmitXmmRegisterOperand(dst, src);
1466}
1467
1468
1469void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
1470 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1471 EmitUint8(0xF2);
1472 EmitUint8(0x0F);
1473 EmitUint8(0x7D);
1474 EmitXmmRegisterOperand(dst, src);
1475}
1476
1477
1478void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
1479 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1480 EmitUint8(0x66);
1481 EmitUint8(0x0F);
1482 EmitUint8(0x7D);
1483 EmitXmmRegisterOperand(dst, src);
1484}
1485
1486
Aart Bikc8e93c72017-05-10 10:49:22 -07001487void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
1488 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1489 EmitUint8(0x66);
1490 EmitUint8(0x0F);
1491 EmitUint8(0x38);
1492 EmitUint8(0x38);
1493 EmitXmmRegisterOperand(dst, src);
1494}
1495
1496void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
1497 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1498 EmitUint8(0x66);
1499 EmitUint8(0x0F);
1500 EmitUint8(0x38);
1501 EmitUint8(0x3C);
1502 EmitXmmRegisterOperand(dst, src);
1503}
1504
1505void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
1506 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1507 EmitUint8(0x66);
1508 EmitUint8(0x0F);
1509 EmitUint8(0xEA);
1510 EmitXmmRegisterOperand(dst, src);
1511}
1512
1513void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
1514 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1515 EmitUint8(0x66);
1516 EmitUint8(0x0F);
1517 EmitUint8(0xEE);
1518 EmitXmmRegisterOperand(dst, src);
1519}
1520
1521void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
1522 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1523 EmitUint8(0x66);
1524 EmitUint8(0x0F);
1525 EmitUint8(0x38);
1526 EmitUint8(0x39);
1527 EmitXmmRegisterOperand(dst, src);
1528}
1529
1530void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
1531 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1532 EmitUint8(0x66);
1533 EmitUint8(0x0F);
1534 EmitUint8(0x38);
1535 EmitUint8(0x3D);
1536 EmitXmmRegisterOperand(dst, src);
1537}
1538
1539void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
1540 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1541 EmitUint8(0x66);
1542 EmitUint8(0x0F);
1543 EmitUint8(0xDA);
1544 EmitXmmRegisterOperand(dst, src);
1545}
1546
1547void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
1548 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1549 EmitUint8(0x66);
1550 EmitUint8(0x0F);
1551 EmitUint8(0xDE);
1552 EmitXmmRegisterOperand(dst, src);
1553}
1554
1555void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
1556 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1557 EmitUint8(0x66);
1558 EmitUint8(0x0F);
1559 EmitUint8(0x38);
1560 EmitUint8(0x3A);
1561 EmitXmmRegisterOperand(dst, src);
1562}
1563
1564void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
1565 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1566 EmitUint8(0x66);
1567 EmitUint8(0x0F);
1568 EmitUint8(0x38);
1569 EmitUint8(0x3E);
1570 EmitXmmRegisterOperand(dst, src);
1571}
1572
1573void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
1574 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1575 EmitUint8(0x66);
1576 EmitUint8(0x0F);
1577 EmitUint8(0x38);
1578 EmitUint8(0x3B);
1579 EmitXmmRegisterOperand(dst, src);
1580}
1581
1582void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
1583 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1584 EmitUint8(0x66);
1585 EmitUint8(0x0F);
1586 EmitUint8(0x38);
1587 EmitUint8(0x3F);
1588 EmitXmmRegisterOperand(dst, src);
1589}
1590
1591void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
1592 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1593 EmitUint8(0x0F);
1594 EmitUint8(0x5D);
1595 EmitXmmRegisterOperand(dst, src);
1596}
1597
1598void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
1599 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1600 EmitUint8(0x0F);
1601 EmitUint8(0x5F);
1602 EmitXmmRegisterOperand(dst, src);
1603}
1604
1605void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
1606 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1607 EmitUint8(0x66);
1608 EmitUint8(0x0F);
1609 EmitUint8(0x5D);
1610 EmitXmmRegisterOperand(dst, src);
1611}
1612
1613void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
1614 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1615 EmitUint8(0x66);
1616 EmitUint8(0x0F);
1617 EmitUint8(0x5F);
1618 EmitXmmRegisterOperand(dst, src);
1619}
Aart Bik67d3fd72017-03-31 15:11:53 -07001620
Aart Bik4b455332017-03-15 11:19:35 -07001621void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
1622 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1623 EmitUint8(0x66);
1624 EmitUint8(0x0F);
1625 EmitUint8(0x74);
1626 EmitXmmRegisterOperand(dst, src);
1627}
1628
1629
1630void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
1631 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1632 EmitUint8(0x66);
1633 EmitUint8(0x0F);
1634 EmitUint8(0x75);
1635 EmitXmmRegisterOperand(dst, src);
1636}
1637
1638
1639void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
1640 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1641 EmitUint8(0x66);
1642 EmitUint8(0x0F);
1643 EmitUint8(0x76);
1644 EmitXmmRegisterOperand(dst, src);
1645}
1646
1647
1648void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
1649 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1650 EmitUint8(0x66);
1651 EmitUint8(0x0F);
1652 EmitUint8(0x38);
1653 EmitUint8(0x29);
1654 EmitXmmRegisterOperand(dst, src);
1655}
1656
1657
Aart Bik8939c642017-04-03 14:09:01 -07001658void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
1659 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1660 EmitUint8(0x66);
1661 EmitUint8(0x0F);
1662 EmitUint8(0x64);
1663 EmitXmmRegisterOperand(dst, src);
1664}
1665
1666
1667void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
1668 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1669 EmitUint8(0x66);
1670 EmitUint8(0x0F);
1671 EmitUint8(0x65);
1672 EmitXmmRegisterOperand(dst, src);
1673}
1674
1675
1676void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
1677 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1678 EmitUint8(0x66);
1679 EmitUint8(0x0F);
1680 EmitUint8(0x66);
1681 EmitXmmRegisterOperand(dst, src);
1682}
1683
1684
1685void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
1686 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1687 EmitUint8(0x66);
1688 EmitUint8(0x0F);
1689 EmitUint8(0x38);
1690 EmitUint8(0x37);
1691 EmitXmmRegisterOperand(dst, src);
1692}
1693
1694
Aart Bik12e06ed2017-01-31 16:11:24 -08001695void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1696 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1697 EmitUint8(0x66);
1698 EmitUint8(0x0F);
1699 EmitUint8(0xC6);
1700 EmitXmmRegisterOperand(dst, src);
1701 EmitUint8(imm.value());
1702}
1703
1704
1705void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1706 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1707 EmitUint8(0x0F);
1708 EmitUint8(0xC6);
1709 EmitXmmRegisterOperand(dst, src);
1710 EmitUint8(imm.value());
1711}
1712
1713
Aart Bik68555e92017-02-13 14:28:45 -08001714void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1716 EmitUint8(0x66);
1717 EmitUint8(0x0F);
1718 EmitUint8(0x70);
1719 EmitXmmRegisterOperand(dst, src);
1720 EmitUint8(imm.value());
1721}
1722
1723
Aart Bike69d7a92017-02-17 11:48:23 -08001724void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1725 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1726 EmitUint8(0x66);
1727 EmitUint8(0x0F);
1728 EmitUint8(0x60);
1729 EmitXmmRegisterOperand(dst, src);
1730}
1731
1732
1733void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1734 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1735 EmitUint8(0x66);
1736 EmitUint8(0x0F);
1737 EmitUint8(0x61);
1738 EmitXmmRegisterOperand(dst, src);
1739}
1740
1741
1742void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1743 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1744 EmitUint8(0x66);
1745 EmitUint8(0x0F);
1746 EmitUint8(0x62);
1747 EmitXmmRegisterOperand(dst, src);
1748}
1749
1750
1751void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1752 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1753 EmitUint8(0x66);
1754 EmitUint8(0x0F);
1755 EmitUint8(0x6C);
1756 EmitXmmRegisterOperand(dst, src);
1757}
1758
1759
Aart Bik3332db82017-08-11 15:10:30 -07001760void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
1761 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1762 EmitUint8(0x66);
1763 EmitUint8(0x0F);
1764 EmitUint8(0x68);
1765 EmitXmmRegisterOperand(dst, src);
1766}
1767
1768
1769void X86Assembler::punpckhwd(XmmRegister dst, XmmRegister src) {
1770 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1771 EmitUint8(0x66);
1772 EmitUint8(0x0F);
1773 EmitUint8(0x69);
1774 EmitXmmRegisterOperand(dst, src);
1775}
1776
1777
1778void X86Assembler::punpckhdq(XmmRegister dst, XmmRegister src) {
1779 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1780 EmitUint8(0x66);
1781 EmitUint8(0x0F);
1782 EmitUint8(0x6A);
1783 EmitXmmRegisterOperand(dst, src);
1784}
1785
1786
1787void X86Assembler::punpckhqdq(XmmRegister dst, XmmRegister src) {
1788 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1789 EmitUint8(0x66);
1790 EmitUint8(0x0F);
1791 EmitUint8(0x6D);
1792 EmitXmmRegisterOperand(dst, src);
1793}
1794
1795
Aart Bike69d7a92017-02-17 11:48:23 -08001796void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1797 DCHECK(shift_count.is_uint8());
1798 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1799 EmitUint8(0x66);
1800 EmitUint8(0x0F);
1801 EmitUint8(0x71);
1802 EmitXmmRegisterOperand(6, reg);
1803 EmitUint8(shift_count.value());
1804}
1805
1806
1807void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1808 DCHECK(shift_count.is_uint8());
1809 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1810 EmitUint8(0x66);
1811 EmitUint8(0x0F);
1812 EmitUint8(0x72);
1813 EmitXmmRegisterOperand(6, reg);
1814 EmitUint8(shift_count.value());
1815}
1816
1817
1818void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1819 DCHECK(shift_count.is_uint8());
1820 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1821 EmitUint8(0x66);
1822 EmitUint8(0x0F);
1823 EmitUint8(0x73);
1824 EmitXmmRegisterOperand(6, reg);
1825 EmitUint8(shift_count.value());
1826}
1827
1828
1829void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1830 DCHECK(shift_count.is_uint8());
1831 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1832 EmitUint8(0x66);
1833 EmitUint8(0x0F);
1834 EmitUint8(0x71);
1835 EmitXmmRegisterOperand(4, reg);
1836 EmitUint8(shift_count.value());
1837}
1838
1839
1840void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1841 DCHECK(shift_count.is_uint8());
1842 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1843 EmitUint8(0x66);
1844 EmitUint8(0x0F);
1845 EmitUint8(0x72);
1846 EmitXmmRegisterOperand(4, reg);
1847 EmitUint8(shift_count.value());
1848}
1849
1850
1851void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1852 DCHECK(shift_count.is_uint8());
1853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1854 EmitUint8(0x66);
1855 EmitUint8(0x0F);
1856 EmitUint8(0x71);
1857 EmitXmmRegisterOperand(2, reg);
1858 EmitUint8(shift_count.value());
1859}
1860
1861
1862void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1863 DCHECK(shift_count.is_uint8());
1864 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1865 EmitUint8(0x66);
1866 EmitUint8(0x0F);
1867 EmitUint8(0x72);
1868 EmitXmmRegisterOperand(2, reg);
1869 EmitUint8(shift_count.value());
1870}
1871
1872
1873void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1874 DCHECK(shift_count.is_uint8());
1875 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1876 EmitUint8(0x66);
1877 EmitUint8(0x0F);
1878 EmitUint8(0x73);
1879 EmitXmmRegisterOperand(2, reg);
1880 EmitUint8(shift_count.value());
1881}
1882
1883
1884void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1885 DCHECK(shift_count.is_uint8());
1886 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1887 EmitUint8(0x66);
1888 EmitUint8(0x0F);
1889 EmitUint8(0x73);
1890 EmitXmmRegisterOperand(3, reg);
1891 EmitUint8(shift_count.value());
1892}
1893
1894
Ian Rogers2c8f6532011-09-02 17:16:34 -07001895void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001896 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1897 EmitUint8(0xDD);
1898 EmitOperand(0, src);
1899}
1900
1901
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001902void X86Assembler::fstl(const Address& dst) {
1903 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1904 EmitUint8(0xDD);
1905 EmitOperand(2, dst);
1906}
1907
1908
Ian Rogers2c8f6532011-09-02 17:16:34 -07001909void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001910 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1911 EmitUint8(0xDD);
1912 EmitOperand(3, dst);
1913}
1914
1915
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001916void X86Assembler::fstsw() {
1917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1918 EmitUint8(0x9B);
1919 EmitUint8(0xDF);
1920 EmitUint8(0xE0);
1921}
1922
1923
Ian Rogers2c8f6532011-09-02 17:16:34 -07001924void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001925 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1926 EmitUint8(0xD9);
1927 EmitOperand(7, dst);
1928}
1929
1930
Ian Rogers2c8f6532011-09-02 17:16:34 -07001931void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001932 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1933 EmitUint8(0xD9);
1934 EmitOperand(5, src);
1935}
1936
1937
Ian Rogers2c8f6532011-09-02 17:16:34 -07001938void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001939 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1940 EmitUint8(0xDF);
1941 EmitOperand(7, dst);
1942}
1943
1944
Ian Rogers2c8f6532011-09-02 17:16:34 -07001945void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001946 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1947 EmitUint8(0xDB);
1948 EmitOperand(3, dst);
1949}
1950
1951
Ian Rogers2c8f6532011-09-02 17:16:34 -07001952void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1954 EmitUint8(0xDF);
1955 EmitOperand(5, src);
1956}
1957
1958
Roland Levillain0a186012015-04-13 17:00:20 +01001959void X86Assembler::filds(const Address& src) {
1960 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1961 EmitUint8(0xDB);
1962 EmitOperand(0, src);
1963}
1964
1965
Ian Rogers2c8f6532011-09-02 17:16:34 -07001966void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001967 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1968 EmitUint8(0xD9);
1969 EmitUint8(0xF7);
1970}
1971
1972
Ian Rogers2c8f6532011-09-02 17:16:34 -07001973void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001974 CHECK_LT(index.value(), 7);
1975 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1976 EmitUint8(0xDD);
1977 EmitUint8(0xC0 + index.value());
1978}
1979
1980
Ian Rogers2c8f6532011-09-02 17:16:34 -07001981void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001982 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1983 EmitUint8(0xD9);
1984 EmitUint8(0xFE);
1985}
1986
1987
Ian Rogers2c8f6532011-09-02 17:16:34 -07001988void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001989 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1990 EmitUint8(0xD9);
1991 EmitUint8(0xFF);
1992}
1993
1994
Ian Rogers2c8f6532011-09-02 17:16:34 -07001995void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001996 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1997 EmitUint8(0xD9);
1998 EmitUint8(0xF2);
1999}
2000
2001
Mark Mendell24f2dfa2015-01-14 19:51:45 -05002002void X86Assembler::fucompp() {
2003 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2004 EmitUint8(0xDA);
2005 EmitUint8(0xE9);
2006}
2007
2008
2009void X86Assembler::fprem() {
2010 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2011 EmitUint8(0xD9);
2012 EmitUint8(0xF8);
2013}
2014
2015
Ian Rogers2c8f6532011-09-02 17:16:34 -07002016void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002017 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2018 EmitUint8(0x87);
2019 EmitRegisterOperand(dst, src);
2020}
2021
Nicolas Geoffray3c049742014-09-24 18:10:46 +01002022
Ian Rogers7caad772012-03-30 01:07:54 -07002023void X86Assembler::xchgl(Register reg, const Address& address) {
2024 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2025 EmitUint8(0x87);
2026 EmitOperand(reg, address);
2027}
2028
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002029
Serguei Katkov3b625932016-05-06 10:24:17 +06002030void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
2031 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2032 EmitUint8(0x80);
2033 EmitOperand(7, address);
2034 EmitUint8(imm.value() & 0xFF);
2035}
2036
2037
Nicolas Geoffray3c049742014-09-24 18:10:46 +01002038void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
2039 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2040 EmitUint8(0x66);
Vladimir Marko29a8d842018-02-13 13:46:15 +00002041 EmitComplex(7, address, imm, /* is_16_op */ true);
Nicolas Geoffray3c049742014-09-24 18:10:46 +01002042}
2043
2044
Ian Rogers2c8f6532011-09-02 17:16:34 -07002045void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002046 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2047 EmitComplex(7, Operand(reg), imm);
2048}
2049
2050
Ian Rogers2c8f6532011-09-02 17:16:34 -07002051void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002052 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2053 EmitUint8(0x3B);
2054 EmitOperand(reg0, Operand(reg1));
2055}
2056
2057
Ian Rogers2c8f6532011-09-02 17:16:34 -07002058void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002059 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2060 EmitUint8(0x3B);
2061 EmitOperand(reg, address);
2062}
2063
2064
Ian Rogers2c8f6532011-09-02 17:16:34 -07002065void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002066 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2067 EmitUint8(0x03);
2068 EmitRegisterOperand(dst, src);
2069}
2070
2071
Ian Rogers2c8f6532011-09-02 17:16:34 -07002072void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002073 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2074 EmitUint8(0x03);
2075 EmitOperand(reg, address);
2076}
2077
2078
Ian Rogers2c8f6532011-09-02 17:16:34 -07002079void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002080 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2081 EmitUint8(0x39);
2082 EmitOperand(reg, address);
2083}
2084
2085
Ian Rogers2c8f6532011-09-02 17:16:34 -07002086void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002087 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2088 EmitComplex(7, address, imm);
2089}
2090
2091
Ian Rogers2c8f6532011-09-02 17:16:34 -07002092void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002093 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2094 EmitUint8(0x85);
2095 EmitRegisterOperand(reg1, reg2);
2096}
2097
2098
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01002099void X86Assembler::testl(Register reg, const Address& address) {
2100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2101 EmitUint8(0x85);
2102 EmitOperand(reg, address);
2103}
2104
2105
Ian Rogers2c8f6532011-09-02 17:16:34 -07002106void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2108 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
2109 // we only test the byte register to keep the encoding short.
2110 if (immediate.is_uint8() && reg < 4) {
2111 // Use zero-extended 8-bit immediate.
2112 if (reg == EAX) {
2113 EmitUint8(0xA8);
2114 } else {
2115 EmitUint8(0xF6);
2116 EmitUint8(0xC0 + reg);
2117 }
2118 EmitUint8(immediate.value() & 0xFF);
2119 } else if (reg == EAX) {
2120 // Use short form if the destination is EAX.
2121 EmitUint8(0xA9);
2122 EmitImmediate(immediate);
2123 } else {
2124 EmitUint8(0xF7);
2125 EmitOperand(0, Operand(reg));
2126 EmitImmediate(immediate);
2127 }
2128}
2129
2130
Vladimir Marko953437b2016-08-24 08:30:46 +00002131void X86Assembler::testb(const Address& dst, const Immediate& imm) {
2132 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2133 EmitUint8(0xF6);
2134 EmitOperand(EAX, dst);
2135 CHECK(imm.is_int8());
2136 EmitUint8(imm.value() & 0xFF);
2137}
2138
2139
2140void X86Assembler::testl(const Address& dst, const Immediate& imm) {
2141 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2142 EmitUint8(0xF7);
2143 EmitOperand(0, dst);
2144 EmitImmediate(imm);
2145}
2146
2147
Ian Rogers2c8f6532011-09-02 17:16:34 -07002148void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2150 EmitUint8(0x23);
2151 EmitOperand(dst, Operand(src));
2152}
2153
2154
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002155void X86Assembler::andl(Register reg, const Address& address) {
2156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2157 EmitUint8(0x23);
2158 EmitOperand(reg, address);
2159}
2160
2161
Ian Rogers2c8f6532011-09-02 17:16:34 -07002162void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002163 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2164 EmitComplex(4, Operand(dst), imm);
2165}
2166
2167
Ian Rogers2c8f6532011-09-02 17:16:34 -07002168void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2170 EmitUint8(0x0B);
2171 EmitOperand(dst, Operand(src));
2172}
2173
2174
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002175void X86Assembler::orl(Register reg, const Address& address) {
2176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2177 EmitUint8(0x0B);
2178 EmitOperand(reg, address);
2179}
2180
2181
Ian Rogers2c8f6532011-09-02 17:16:34 -07002182void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2184 EmitComplex(1, Operand(dst), imm);
2185}
2186
2187
Ian Rogers2c8f6532011-09-02 17:16:34 -07002188void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2190 EmitUint8(0x33);
2191 EmitOperand(dst, Operand(src));
2192}
2193
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002194
2195void X86Assembler::xorl(Register reg, const Address& address) {
2196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2197 EmitUint8(0x33);
2198 EmitOperand(reg, address);
2199}
2200
2201
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01002202void X86Assembler::xorl(Register dst, const Immediate& imm) {
2203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2204 EmitComplex(6, Operand(dst), imm);
2205}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002206
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002207
Ian Rogers2c8f6532011-09-02 17:16:34 -07002208void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002209 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2210 EmitComplex(0, Operand(reg), imm);
2211}
2212
2213
Ian Rogers2c8f6532011-09-02 17:16:34 -07002214void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002215 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2216 EmitUint8(0x01);
2217 EmitOperand(reg, address);
2218}
2219
2220
Ian Rogers2c8f6532011-09-02 17:16:34 -07002221void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2223 EmitComplex(0, address, imm);
2224}
2225
2226
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002227void X86Assembler::addw(const Address& address, const Immediate& imm) {
2228 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2229 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
2230 EmitUint8(0x66);
2231 EmitComplex(0, address, imm, /* is_16_op */ true);
2232}
2233
2234
Ian Rogers2c8f6532011-09-02 17:16:34 -07002235void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002236 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2237 EmitComplex(2, Operand(reg), imm);
2238}
2239
2240
Ian Rogers2c8f6532011-09-02 17:16:34 -07002241void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002242 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2243 EmitUint8(0x13);
2244 EmitOperand(dst, Operand(src));
2245}
2246
2247
Ian Rogers2c8f6532011-09-02 17:16:34 -07002248void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002249 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2250 EmitUint8(0x13);
2251 EmitOperand(dst, address);
2252}
2253
2254
Ian Rogers2c8f6532011-09-02 17:16:34 -07002255void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002256 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2257 EmitUint8(0x2B);
2258 EmitOperand(dst, Operand(src));
2259}
2260
2261
Ian Rogers2c8f6532011-09-02 17:16:34 -07002262void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002263 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2264 EmitComplex(5, Operand(reg), imm);
2265}
2266
2267
Ian Rogers2c8f6532011-09-02 17:16:34 -07002268void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002269 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2270 EmitUint8(0x2B);
2271 EmitOperand(reg, address);
2272}
2273
2274
Mark Mendell09ed1a32015-03-25 08:30:06 -04002275void X86Assembler::subl(const Address& address, Register reg) {
2276 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2277 EmitUint8(0x29);
2278 EmitOperand(reg, address);
2279}
2280
2281
Ian Rogers2c8f6532011-09-02 17:16:34 -07002282void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2284 EmitUint8(0x99);
2285}
2286
2287
Ian Rogers2c8f6532011-09-02 17:16:34 -07002288void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002289 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2290 EmitUint8(0xF7);
2291 EmitUint8(0xF8 | reg);
2292}
2293
2294
Ian Rogers2c8f6532011-09-02 17:16:34 -07002295void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2297 EmitUint8(0x0F);
2298 EmitUint8(0xAF);
2299 EmitOperand(dst, Operand(src));
2300}
2301
2302
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002303void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002305 // See whether imm can be represented as a sign-extended 8bit value.
2306 int32_t v32 = static_cast<int32_t>(imm.value());
2307 if (IsInt<8>(v32)) {
2308 // Sign-extension works.
2309 EmitUint8(0x6B);
2310 EmitOperand(dst, Operand(src));
2311 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
2312 } else {
2313 // Not representable, use full immediate.
2314 EmitUint8(0x69);
2315 EmitOperand(dst, Operand(src));
2316 EmitImmediate(imm);
2317 }
2318}
2319
2320
2321void X86Assembler::imull(Register reg, const Immediate& imm) {
2322 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002323}
2324
2325
Ian Rogers2c8f6532011-09-02 17:16:34 -07002326void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002327 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2328 EmitUint8(0x0F);
2329 EmitUint8(0xAF);
2330 EmitOperand(reg, address);
2331}
2332
2333
Ian Rogers2c8f6532011-09-02 17:16:34 -07002334void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002335 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2336 EmitUint8(0xF7);
2337 EmitOperand(5, Operand(reg));
2338}
2339
2340
Ian Rogers2c8f6532011-09-02 17:16:34 -07002341void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002342 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2343 EmitUint8(0xF7);
2344 EmitOperand(5, address);
2345}
2346
2347
Ian Rogers2c8f6532011-09-02 17:16:34 -07002348void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002349 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2350 EmitUint8(0xF7);
2351 EmitOperand(4, Operand(reg));
2352}
2353
2354
Ian Rogers2c8f6532011-09-02 17:16:34 -07002355void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002356 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2357 EmitUint8(0xF7);
2358 EmitOperand(4, address);
2359}
2360
2361
Ian Rogers2c8f6532011-09-02 17:16:34 -07002362void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002363 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2364 EmitUint8(0x1B);
2365 EmitOperand(dst, Operand(src));
2366}
2367
2368
Ian Rogers2c8f6532011-09-02 17:16:34 -07002369void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2371 EmitComplex(3, Operand(reg), imm);
2372}
2373
2374
Ian Rogers2c8f6532011-09-02 17:16:34 -07002375void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002376 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2377 EmitUint8(0x1B);
2378 EmitOperand(dst, address);
2379}
2380
2381
Mark Mendell09ed1a32015-03-25 08:30:06 -04002382void X86Assembler::sbbl(const Address& address, Register src) {
2383 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2384 EmitUint8(0x19);
2385 EmitOperand(src, address);
2386}
2387
2388
Ian Rogers2c8f6532011-09-02 17:16:34 -07002389void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002390 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2391 EmitUint8(0x40 + reg);
2392}
2393
2394
Ian Rogers2c8f6532011-09-02 17:16:34 -07002395void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002396 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2397 EmitUint8(0xFF);
2398 EmitOperand(0, address);
2399}
2400
2401
Ian Rogers2c8f6532011-09-02 17:16:34 -07002402void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002403 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2404 EmitUint8(0x48 + reg);
2405}
2406
2407
Ian Rogers2c8f6532011-09-02 17:16:34 -07002408void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002409 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2410 EmitUint8(0xFF);
2411 EmitOperand(1, address);
2412}
2413
2414
Ian Rogers2c8f6532011-09-02 17:16:34 -07002415void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002416 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002417}
2418
2419
Ian Rogers2c8f6532011-09-02 17:16:34 -07002420void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002421 EmitGenericShift(4, Operand(operand), shifter);
2422}
2423
2424
2425void X86Assembler::shll(const Address& address, const Immediate& imm) {
2426 EmitGenericShift(4, address, imm);
2427}
2428
2429
2430void X86Assembler::shll(const Address& address, Register shifter) {
2431 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002432}
2433
2434
Ian Rogers2c8f6532011-09-02 17:16:34 -07002435void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002436 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002437}
2438
2439
Ian Rogers2c8f6532011-09-02 17:16:34 -07002440void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002441 EmitGenericShift(5, Operand(operand), shifter);
2442}
2443
2444
2445void X86Assembler::shrl(const Address& address, const Immediate& imm) {
2446 EmitGenericShift(5, address, imm);
2447}
2448
2449
2450void X86Assembler::shrl(const Address& address, Register shifter) {
2451 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002452}
2453
2454
Ian Rogers2c8f6532011-09-02 17:16:34 -07002455void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002456 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002457}
2458
2459
Ian Rogers2c8f6532011-09-02 17:16:34 -07002460void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002461 EmitGenericShift(7, Operand(operand), shifter);
2462}
2463
2464
2465void X86Assembler::sarl(const Address& address, const Immediate& imm) {
2466 EmitGenericShift(7, address, imm);
2467}
2468
2469
2470void X86Assembler::sarl(const Address& address, Register shifter) {
2471 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002472}
2473
2474
Calin Juravle9aec02f2014-11-18 23:06:35 +00002475void X86Assembler::shld(Register dst, Register src, Register shifter) {
2476 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002477 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2478 EmitUint8(0x0F);
2479 EmitUint8(0xA5);
2480 EmitRegisterOperand(src, dst);
2481}
2482
2483
Mark P Mendell73945692015-04-29 14:56:17 +00002484void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
2485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2486 EmitUint8(0x0F);
2487 EmitUint8(0xA4);
2488 EmitRegisterOperand(src, dst);
2489 EmitUint8(imm.value() & 0xFF);
2490}
2491
2492
Calin Juravle9aec02f2014-11-18 23:06:35 +00002493void X86Assembler::shrd(Register dst, Register src, Register shifter) {
2494 DCHECK_EQ(ECX, shifter);
2495 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2496 EmitUint8(0x0F);
2497 EmitUint8(0xAD);
2498 EmitRegisterOperand(src, dst);
2499}
2500
2501
Mark P Mendell73945692015-04-29 14:56:17 +00002502void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
2503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2504 EmitUint8(0x0F);
2505 EmitUint8(0xAC);
2506 EmitRegisterOperand(src, dst);
2507 EmitUint8(imm.value() & 0xFF);
2508}
2509
2510
Mark Mendellbcee0922015-09-15 21:45:01 -04002511void X86Assembler::roll(Register reg, const Immediate& imm) {
2512 EmitGenericShift(0, Operand(reg), imm);
2513}
2514
2515
2516void X86Assembler::roll(Register operand, Register shifter) {
2517 EmitGenericShift(0, Operand(operand), shifter);
2518}
2519
2520
2521void X86Assembler::rorl(Register reg, const Immediate& imm) {
2522 EmitGenericShift(1, Operand(reg), imm);
2523}
2524
2525
2526void X86Assembler::rorl(Register operand, Register shifter) {
2527 EmitGenericShift(1, Operand(operand), shifter);
2528}
2529
2530
Ian Rogers2c8f6532011-09-02 17:16:34 -07002531void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002532 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2533 EmitUint8(0xF7);
2534 EmitOperand(3, Operand(reg));
2535}
2536
2537
Ian Rogers2c8f6532011-09-02 17:16:34 -07002538void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002539 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2540 EmitUint8(0xF7);
2541 EmitUint8(0xD0 | reg);
2542}
2543
2544
Ian Rogers2c8f6532011-09-02 17:16:34 -07002545void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002546 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2547 EmitUint8(0xC8);
2548 CHECK(imm.is_uint16());
2549 EmitUint8(imm.value() & 0xFF);
2550 EmitUint8((imm.value() >> 8) & 0xFF);
2551 EmitUint8(0x00);
2552}
2553
2554
Ian Rogers2c8f6532011-09-02 17:16:34 -07002555void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002556 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2557 EmitUint8(0xC9);
2558}
2559
2560
Ian Rogers2c8f6532011-09-02 17:16:34 -07002561void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2563 EmitUint8(0xC3);
2564}
2565
2566
Ian Rogers2c8f6532011-09-02 17:16:34 -07002567void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002568 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2569 EmitUint8(0xC2);
2570 CHECK(imm.is_uint16());
2571 EmitUint8(imm.value() & 0xFF);
2572 EmitUint8((imm.value() >> 8) & 0xFF);
2573}
2574
2575
2576
Ian Rogers2c8f6532011-09-02 17:16:34 -07002577void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002578 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2579 EmitUint8(0x90);
2580}
2581
2582
Ian Rogers2c8f6532011-09-02 17:16:34 -07002583void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002584 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2585 EmitUint8(0xCC);
2586}
2587
2588
Ian Rogers2c8f6532011-09-02 17:16:34 -07002589void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002590 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2591 EmitUint8(0xF4);
2592}
2593
2594
Ian Rogers2c8f6532011-09-02 17:16:34 -07002595void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002596 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2597 if (label->IsBound()) {
2598 static const int kShortSize = 2;
2599 static const int kLongSize = 6;
2600 int offset = label->Position() - buffer_.Size();
2601 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002602 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002603 EmitUint8(0x70 + condition);
2604 EmitUint8((offset - kShortSize) & 0xFF);
2605 } else {
2606 EmitUint8(0x0F);
2607 EmitUint8(0x80 + condition);
2608 EmitInt32(offset - kLongSize);
2609 }
2610 } else {
2611 EmitUint8(0x0F);
2612 EmitUint8(0x80 + condition);
2613 EmitLabelLink(label);
2614 }
2615}
2616
2617
Mark Mendell73f455e2015-08-21 09:30:05 -04002618void X86Assembler::j(Condition condition, NearLabel* label) {
2619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2620 if (label->IsBound()) {
2621 static const int kShortSize = 2;
2622 int offset = label->Position() - buffer_.Size();
2623 CHECK_LE(offset, 0);
2624 CHECK(IsInt<8>(offset - kShortSize));
2625 EmitUint8(0x70 + condition);
2626 EmitUint8((offset - kShortSize) & 0xFF);
2627 } else {
2628 EmitUint8(0x70 + condition);
2629 EmitLabelLink(label);
2630 }
2631}
2632
2633
2634void X86Assembler::jecxz(NearLabel* label) {
2635 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2636 if (label->IsBound()) {
2637 static const int kShortSize = 2;
2638 int offset = label->Position() - buffer_.Size();
2639 CHECK_LE(offset, 0);
2640 CHECK(IsInt<8>(offset - kShortSize));
2641 EmitUint8(0xE3);
2642 EmitUint8((offset - kShortSize) & 0xFF);
2643 } else {
2644 EmitUint8(0xE3);
2645 EmitLabelLink(label);
2646 }
2647}
2648
2649
Ian Rogers2c8f6532011-09-02 17:16:34 -07002650void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002651 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2652 EmitUint8(0xFF);
2653 EmitRegisterOperand(4, reg);
2654}
2655
Ian Rogers7caad772012-03-30 01:07:54 -07002656void X86Assembler::jmp(const Address& address) {
2657 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2658 EmitUint8(0xFF);
2659 EmitOperand(4, address);
2660}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002661
Ian Rogers2c8f6532011-09-02 17:16:34 -07002662void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002663 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2664 if (label->IsBound()) {
2665 static const int kShortSize = 2;
2666 static const int kLongSize = 5;
2667 int offset = label->Position() - buffer_.Size();
2668 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002669 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002670 EmitUint8(0xEB);
2671 EmitUint8((offset - kShortSize) & 0xFF);
2672 } else {
2673 EmitUint8(0xE9);
2674 EmitInt32(offset - kLongSize);
2675 }
2676 } else {
2677 EmitUint8(0xE9);
2678 EmitLabelLink(label);
2679 }
2680}
2681
2682
Mark Mendell73f455e2015-08-21 09:30:05 -04002683void X86Assembler::jmp(NearLabel* label) {
2684 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2685 if (label->IsBound()) {
2686 static const int kShortSize = 2;
2687 int offset = label->Position() - buffer_.Size();
2688 CHECK_LE(offset, 0);
2689 CHECK(IsInt<8>(offset - kShortSize));
2690 EmitUint8(0xEB);
2691 EmitUint8((offset - kShortSize) & 0xFF);
2692 } else {
2693 EmitUint8(0xEB);
2694 EmitLabelLink(label);
2695 }
2696}
2697
2698
jessicahandojob03d6402016-09-07 12:16:53 -07002699void X86Assembler::repne_scasb() {
2700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2701 EmitUint8(0xF2);
2702 EmitUint8(0xAE);
2703}
2704
2705
Andreas Gampe21030dd2015-05-07 14:46:15 -07002706void X86Assembler::repne_scasw() {
2707 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2708 EmitUint8(0x66);
2709 EmitUint8(0xF2);
2710 EmitUint8(0xAF);
2711}
2712
2713
jessicahandojob03d6402016-09-07 12:16:53 -07002714void X86Assembler::repe_cmpsb() {
2715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2716 EmitUint8(0xF2);
2717 EmitUint8(0xA6);
2718}
2719
2720
agicsaki71311f82015-07-27 11:34:13 -07002721void X86Assembler::repe_cmpsw() {
2722 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2723 EmitUint8(0x66);
2724 EmitUint8(0xF3);
2725 EmitUint8(0xA7);
2726}
2727
2728
agicsaki970abfb2015-07-31 10:31:14 -07002729void X86Assembler::repe_cmpsl() {
2730 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2731 EmitUint8(0xF3);
2732 EmitUint8(0xA7);
2733}
2734
2735
jessicahandojob03d6402016-09-07 12:16:53 -07002736void X86Assembler::rep_movsb() {
2737 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2738 EmitUint8(0xF3);
2739 EmitUint8(0xA4);
2740}
2741
2742
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002743void X86Assembler::rep_movsw() {
2744 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2745 EmitUint8(0x66);
2746 EmitUint8(0xF3);
2747 EmitUint8(0xA5);
2748}
2749
2750
Ian Rogers2c8f6532011-09-02 17:16:34 -07002751X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002752 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2753 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002754 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002755}
2756
2757
Ian Rogers2c8f6532011-09-02 17:16:34 -07002758void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002759 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2760 EmitUint8(0x0F);
2761 EmitUint8(0xB1);
2762 EmitOperand(reg, address);
2763}
2764
Mark Mendell58d25fd2015-04-03 14:52:31 -04002765
2766void X86Assembler::cmpxchg8b(const Address& address) {
2767 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2768 EmitUint8(0x0F);
2769 EmitUint8(0xC7);
2770 EmitOperand(1, address);
2771}
2772
2773
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002774void X86Assembler::mfence() {
2775 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2776 EmitUint8(0x0F);
2777 EmitUint8(0xAE);
2778 EmitUint8(0xF0);
2779}
2780
Ian Rogers2c8f6532011-09-02 17:16:34 -07002781X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002782 // TODO: fs is a prefix and not an instruction
2783 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2784 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002785 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002786}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002787
Ian Rogersbefbd572014-03-06 01:13:39 -08002788X86Assembler* X86Assembler::gs() {
2789 // TODO: fs is a prefix and not an instruction
2790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2791 EmitUint8(0x65);
2792 return this;
2793}
2794
Ian Rogers2c8f6532011-09-02 17:16:34 -07002795void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002796 int value = imm.value();
2797 if (value > 0) {
2798 if (value == 1) {
2799 incl(reg);
2800 } else if (value != 0) {
2801 addl(reg, imm);
2802 }
2803 } else if (value < 0) {
2804 value = -value;
2805 if (value == 1) {
2806 decl(reg);
2807 } else if (value != 0) {
2808 subl(reg, Immediate(value));
2809 }
2810 }
2811}
2812
2813
Roland Levillain647b9ed2014-11-27 12:06:00 +00002814void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2815 // TODO: Need to have a code constants table.
2816 pushl(Immediate(High32Bits(value)));
2817 pushl(Immediate(Low32Bits(value)));
2818 movsd(dst, Address(ESP, 0));
2819 addl(ESP, Immediate(2 * sizeof(int32_t)));
2820}
2821
2822
Ian Rogers2c8f6532011-09-02 17:16:34 -07002823void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002824 // TODO: Need to have a code constants table.
2825 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002826 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002827}
2828
2829
Ian Rogers2c8f6532011-09-02 17:16:34 -07002830void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002831 CHECK(IsPowerOfTwo(alignment));
2832 // Emit nop instruction until the real position is aligned.
2833 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2834 nop();
2835 }
2836}
2837
2838
Ian Rogers2c8f6532011-09-02 17:16:34 -07002839void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002840 int bound = buffer_.Size();
2841 CHECK(!label->IsBound()); // Labels can only be bound once.
2842 while (label->IsLinked()) {
2843 int position = label->LinkPosition();
2844 int next = buffer_.Load<int32_t>(position);
2845 buffer_.Store<int32_t>(position, bound - (position + 4));
2846 label->position_ = next;
2847 }
2848 label->BindTo(bound);
2849}
2850
2851
Mark Mendell73f455e2015-08-21 09:30:05 -04002852void X86Assembler::Bind(NearLabel* label) {
2853 int bound = buffer_.Size();
2854 CHECK(!label->IsBound()); // Labels can only be bound once.
2855 while (label->IsLinked()) {
2856 int position = label->LinkPosition();
2857 uint8_t delta = buffer_.Load<uint8_t>(position);
2858 int offset = bound - (position + 1);
2859 CHECK(IsInt<8>(offset));
2860 buffer_.Store<int8_t>(position, offset);
2861 label->position_ = delta != 0u ? label->position_ - delta : 0;
2862 }
2863 label->BindTo(bound);
2864}
2865
2866
Ian Rogers44fb0d02012-03-23 16:46:24 -07002867void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2868 CHECK_GE(reg_or_opcode, 0);
2869 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002870 const int length = operand.length_;
2871 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002872 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002873 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002874 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002875 // Emit the rest of the encoded operand.
2876 for (int i = 1; i < length; i++) {
2877 EmitUint8(operand.encoding_[i]);
2878 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002879 AssemblerFixup* fixup = operand.GetFixup();
2880 if (fixup != nullptr) {
2881 EmitFixup(fixup);
2882 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002883}
2884
2885
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002886void X86Assembler::EmitImmediate(const Immediate& imm, bool is_16_op) {
2887 if (is_16_op) {
2888 EmitUint8(imm.value() & 0xFF);
2889 EmitUint8(imm.value() >> 8);
2890 } else {
2891 EmitInt32(imm.value());
2892 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002893}
2894
2895
Ian Rogers44fb0d02012-03-23 16:46:24 -07002896void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002897 const Operand& operand,
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002898 const Immediate& immediate,
2899 bool is_16_op) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002900 CHECK_GE(reg_or_opcode, 0);
2901 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002902 if (immediate.is_int8()) {
2903 // Use sign-extended 8-bit immediate.
2904 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002905 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002906 EmitUint8(immediate.value() & 0xFF);
2907 } else if (operand.IsRegister(EAX)) {
2908 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002909 EmitUint8(0x05 + (reg_or_opcode << 3));
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002910 EmitImmediate(immediate, is_16_op);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002911 } else {
2912 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002913 EmitOperand(reg_or_opcode, operand);
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002914 EmitImmediate(immediate, is_16_op);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002915 }
2916}
2917
2918
Ian Rogers2c8f6532011-09-02 17:16:34 -07002919void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002920 if (label->IsBound()) {
2921 int offset = label->Position() - buffer_.Size();
2922 CHECK_LE(offset, 0);
2923 EmitInt32(offset - instruction_size);
2924 } else {
2925 EmitLabelLink(label);
2926 }
2927}
2928
2929
Ian Rogers2c8f6532011-09-02 17:16:34 -07002930void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002931 CHECK(!label->IsBound());
2932 int position = buffer_.Size();
2933 EmitInt32(label->position_);
2934 label->LinkTo(position);
2935}
2936
2937
Mark Mendell73f455e2015-08-21 09:30:05 -04002938void X86Assembler::EmitLabelLink(NearLabel* label) {
2939 CHECK(!label->IsBound());
2940 int position = buffer_.Size();
2941 if (label->IsLinked()) {
2942 // Save the delta in the byte that we have to play with.
2943 uint32_t delta = position - label->LinkPosition();
2944 CHECK(IsUint<8>(delta));
2945 EmitUint8(delta & 0xFF);
2946 } else {
2947 EmitUint8(0);
2948 }
2949 label->LinkTo(position);
2950}
2951
2952
Gupta Kumar, Sanjiv61908882018-06-29 13:06:35 +05302953uint8_t X86Assembler::EmitVexByteZero(bool is_two_byte) {
2954 uint8_t vex_zero = 0xC0;
2955 if (!is_two_byte) {
2956 vex_zero |= 0xC4;
2957 } else {
2958 vex_zero |= 0xC5;
2959 }
2960 return vex_zero;
2961}
2962
2963uint8_t X86Assembler::EmitVexByte1(bool r, bool x, bool b, int mmmmm ) {
2964 // VEX Byte 1.
2965 uint8_t vex_prefix = 0;
2966 if (!r) {
2967 vex_prefix |= 0x80; // VEX.R .
2968 }
2969 if (!x) {
2970 vex_prefix |= 0x40; // VEX.X .
2971 }
2972 if (!b) {
2973 vex_prefix |= 0x20; // VEX.B .
2974 }
2975
2976 // VEX.mmmmm.
2977 switch (mmmmm) {
2978 case 1:
2979 // Implied 0F leading opcode byte.
2980 vex_prefix |= 0x01;
2981 break;
2982 case 2:
2983 // Implied leading 0F 38 opcode byte.
2984 vex_prefix |= 0x02;
2985 break;
2986 case 3:
2987 // Implied leading OF 3A opcode byte.
2988 vex_prefix |= 0x03;
2989 break;
2990 default:
2991 LOG(FATAL) << "unknown opcode bytes";
2992 }
2993 return vex_prefix;
2994}
2995
2996uint8_t X86Assembler::EmitVexByte2(bool w, int l, X86ManagedRegister operand, int pp) {
2997 uint8_t vex_prefix = 0;
2998 // VEX Byte 2.
2999 if (w) {
3000 vex_prefix |= 0x80;
3001 }
3002
3003 // VEX.vvvv.
3004 if (operand.IsXmmRegister()) {
3005 XmmRegister vvvv = operand.AsXmmRegister();
3006 int inverted_reg = 15-static_cast<int>(vvvv);
3007 uint8_t reg = static_cast<uint8_t>(inverted_reg);
3008 vex_prefix |= ((reg & 0x0F) << 3);
3009 } else if (operand.IsCpuRegister()) {
3010 Register vvvv = operand.AsCpuRegister();
3011 int inverted_reg = 15 - static_cast<int>(vvvv);
3012 uint8_t reg = static_cast<uint8_t>(inverted_reg);
3013 vex_prefix |= ((reg & 0x0F) << 3);
3014 }
3015
3016 // VEX.L.
3017 if (l == 256) {
3018 vex_prefix |= 0x04;
3019 }
3020
3021 // VEX.pp.
3022 switch (pp) {
3023 case 0:
3024 // SIMD Pefix - None.
3025 vex_prefix |= 0x00;
3026 break;
3027 case 1:
3028 // SIMD Prefix - 66.
3029 vex_prefix |= 0x01;
3030 break;
3031 case 2:
3032 // SIMD Prefix - F3.
3033 vex_prefix |= 0x02;
3034 break;
3035 case 3:
3036 // SIMD Prefix - F2.
3037 vex_prefix |= 0x03;
3038 break;
3039 default:
3040 LOG(FATAL) << "unknown SIMD Prefix";
3041 }
3042
3043 return vex_prefix;
3044}
3045
Ian Rogers44fb0d02012-03-23 16:46:24 -07003046void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00003047 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07003048 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07003049 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3050 CHECK(imm.is_int8());
3051 if (imm.value() == 1) {
3052 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00003053 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07003054 } else {
3055 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00003056 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07003057 EmitUint8(imm.value() & 0xFF);
3058 }
3059}
3060
3061
Ian Rogers44fb0d02012-03-23 16:46:24 -07003062void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00003063 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07003064 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07003065 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3066 CHECK_EQ(shifter, ECX);
3067 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00003068 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07003069}
3070
Mark Mendell0616ae02015-04-17 12:49:27 -04003071void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01003072 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04003073 // Generate the data for the literal area.
3074 for (size_t i = 0, e = area.size(); i < e; i++) {
3075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3076 EmitInt32(area[i]);
3077 }
3078}
3079
Mark Mendell805b3b52015-09-18 14:10:29 -04003080size_t ConstantArea::AppendInt32(int32_t v) {
3081 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04003082 buffer_.push_back(v);
3083 return result;
3084}
3085
Mark Mendell805b3b52015-09-18 14:10:29 -04003086size_t ConstantArea::AddInt32(int32_t v) {
3087 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
3088 if (v == buffer_[i]) {
3089 return i * elem_size_;
3090 }
3091 }
3092
3093 // Didn't match anything.
3094 return AppendInt32(v);
3095}
3096
3097size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04003098 int32_t v_low = Low32Bits(v);
3099 int32_t v_high = High32Bits(v);
3100 if (buffer_.size() > 1) {
3101 // Ensure we don't pass the end of the buffer.
3102 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
3103 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04003104 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04003105 }
3106 }
3107 }
3108
3109 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04003110 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04003111 buffer_.push_back(v_low);
3112 buffer_.push_back(v_high);
3113 return result;
3114}
3115
Mark Mendell805b3b52015-09-18 14:10:29 -04003116size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04003117 // Treat the value as a 64-bit integer value.
3118 return AddInt64(bit_cast<int64_t, double>(v));
3119}
3120
Mark Mendell805b3b52015-09-18 14:10:29 -04003121size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04003122 // Treat the value as a 32-bit integer value.
3123 return AddInt32(bit_cast<int32_t, float>(v));
3124}
3125
Ian Rogers2c8f6532011-09-02 17:16:34 -07003126} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07003127} // namespace art