blob: 86f9010ea324322e28eec0962b6c7f1e092e0579 [file] [log] [blame]
Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
David Sehr1ce2b3b2018-04-05 11:02:03 -070020#include "base/memory_region.h"
Ian Rogers166db042013-07-26 12:05:57 -070021#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Aart Bikcaa31e72017-09-14 17:08:50 -070035std::ostream& operator<<(std::ostream& os, const Address& addr) {
36 switch (addr.mod()) {
37 case 0:
Aart Bikf7754e82017-09-20 10:33:06 -070038 if (addr.rm() != ESP || addr.index() == ESP) {
39 return os << "(%" << addr.rm() << ")";
40 } else if (addr.base() == EBP) {
41 return os << static_cast<int>(addr.disp32()) << "(,%" << addr.index()
42 << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070043 }
Aart Bikf7754e82017-09-20 10:33:06 -070044 return os << "(%" << addr.base() << ",%" << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070045 case 1:
Aart Bikf7754e82017-09-20 10:33:06 -070046 if (addr.rm() != ESP || addr.index() == ESP) {
47 return os << static_cast<int>(addr.disp8()) << "(%" << addr.rm() << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070048 }
Aart Bikf7754e82017-09-20 10:33:06 -070049 return os << static_cast<int>(addr.disp8()) << "(%" << addr.base() << ",%"
50 << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070051 case 2:
Aart Bikf7754e82017-09-20 10:33:06 -070052 if (addr.rm() != ESP || addr.index() == ESP) {
53 return os << static_cast<int>(addr.disp32()) << "(%" << addr.rm() << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070054 }
Aart Bikf7754e82017-09-20 10:33:06 -070055 return os << static_cast<int>(addr.disp32()) << "(%" << addr.base() << ",%"
56 << addr.index() << "," << (1 << addr.scale()) << ")";
Aart Bikcaa31e72017-09-14 17:08:50 -070057 default:
58 return os << "<address?>";
59 }
60}
61
Ian Rogers2c8f6532011-09-02 17:16:34 -070062void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070063 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
64 EmitUint8(0xFF);
65 EmitRegisterOperand(2, reg);
66}
67
68
Ian Rogers2c8f6532011-09-02 17:16:34 -070069void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070070 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71 EmitUint8(0xFF);
72 EmitOperand(2, address);
73}
74
75
Ian Rogers2c8f6532011-09-02 17:16:34 -070076void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070077 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
78 EmitUint8(0xE8);
79 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000080 // Offset by one because we already have emitted the opcode.
81 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082}
83
84
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000085void X86Assembler::call(const ExternalLabel& label) {
86 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
87 intptr_t call_start = buffer_.GetPosition();
88 EmitUint8(0xE8);
89 EmitInt32(label.address());
90 static const intptr_t kCallExternalLabelSize = 5;
91 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
92}
93
94
Ian Rogers2c8f6532011-09-02 17:16:34 -070095void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
97 EmitUint8(0x50 + reg);
98}
99
100
Ian Rogers2c8f6532011-09-02 17:16:34 -0700101void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700102 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
103 EmitUint8(0xFF);
104 EmitOperand(6, address);
105}
106
107
Ian Rogers2c8f6532011-09-02 17:16:34 -0700108void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700109 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -0700110 if (imm.is_int8()) {
111 EmitUint8(0x6A);
112 EmitUint8(imm.value() & 0xFF);
113 } else {
114 EmitUint8(0x68);
115 EmitImmediate(imm);
116 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x58 + reg);
123}
124
125
Ian Rogers2c8f6532011-09-02 17:16:34 -0700126void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700127 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
128 EmitUint8(0x8F);
129 EmitOperand(0, address);
130}
131
132
Ian Rogers2c8f6532011-09-02 17:16:34 -0700133void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700134 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
135 EmitUint8(0xB8 + dst);
136 EmitImmediate(imm);
137}
138
139
Ian Rogers2c8f6532011-09-02 17:16:34 -0700140void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700141 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
142 EmitUint8(0x89);
143 EmitRegisterOperand(src, dst);
144}
145
146
Ian Rogers2c8f6532011-09-02 17:16:34 -0700147void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
149 EmitUint8(0x8B);
150 EmitOperand(dst, src);
151}
152
153
Ian Rogers2c8f6532011-09-02 17:16:34 -0700154void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700155 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
156 EmitUint8(0x89);
157 EmitOperand(src, dst);
158}
159
160
Ian Rogers2c8f6532011-09-02 17:16:34 -0700161void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0xC7);
164 EmitOperand(0, dst);
165 EmitImmediate(imm);
166}
167
Ian Rogersbdb03912011-09-14 00:55:44 -0700168void X86Assembler::movl(const Address& dst, Label* lbl) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0xC7);
171 EmitOperand(0, dst);
172 EmitLabel(lbl, dst.length_ + 5);
173}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700174
Mark Mendell7a08fb52015-07-15 14:09:35 -0400175void X86Assembler::movntl(const Address& dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xC3);
179 EmitOperand(src, dst);
180}
181
Mark Mendell09ed1a32015-03-25 08:30:06 -0400182void X86Assembler::bswapl(Register dst) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xC8 + dst);
186}
187
Mark Mendellbcee0922015-09-15 21:45:01 -0400188void X86Assembler::bsfl(Register dst, Register src) {
189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
190 EmitUint8(0x0F);
191 EmitUint8(0xBC);
192 EmitRegisterOperand(dst, src);
193}
194
195void X86Assembler::bsfl(Register dst, const Address& src) {
196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
197 EmitUint8(0x0F);
198 EmitUint8(0xBC);
199 EmitOperand(dst, src);
200}
201
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400202void X86Assembler::bsrl(Register dst, Register src) {
203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
204 EmitUint8(0x0F);
205 EmitUint8(0xBD);
206 EmitRegisterOperand(dst, src);
207}
208
209void X86Assembler::bsrl(Register dst, const Address& src) {
210 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
211 EmitUint8(0x0F);
212 EmitUint8(0xBD);
213 EmitOperand(dst, src);
214}
215
Aart Bikc39dac12016-01-21 08:59:48 -0800216void X86Assembler::popcntl(Register dst, Register src) {
217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
218 EmitUint8(0xF3);
219 EmitUint8(0x0F);
220 EmitUint8(0xB8);
221 EmitRegisterOperand(dst, src);
222}
223
224void X86Assembler::popcntl(Register dst, const Address& src) {
225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
226 EmitUint8(0xF3);
227 EmitUint8(0x0F);
228 EmitUint8(0xB8);
229 EmitOperand(dst, src);
230}
231
Ian Rogers2c8f6532011-09-02 17:16:34 -0700232void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700233 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
234 EmitUint8(0x0F);
235 EmitUint8(0xB6);
236 EmitRegisterOperand(dst, src);
237}
238
239
Ian Rogers2c8f6532011-09-02 17:16:34 -0700240void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700241 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
242 EmitUint8(0x0F);
243 EmitUint8(0xB6);
244 EmitOperand(dst, src);
245}
246
247
Ian Rogers2c8f6532011-09-02 17:16:34 -0700248void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700249 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
250 EmitUint8(0x0F);
251 EmitUint8(0xBE);
252 EmitRegisterOperand(dst, src);
253}
254
255
Ian Rogers2c8f6532011-09-02 17:16:34 -0700256void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700257 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
258 EmitUint8(0x0F);
259 EmitUint8(0xBE);
260 EmitOperand(dst, src);
261}
262
263
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700264void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700265 LOG(FATAL) << "Use movzxb or movsxb instead.";
266}
267
268
Ian Rogers2c8f6532011-09-02 17:16:34 -0700269void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700270 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
271 EmitUint8(0x88);
272 EmitOperand(src, dst);
273}
274
275
Ian Rogers2c8f6532011-09-02 17:16:34 -0700276void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700277 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
278 EmitUint8(0xC6);
279 EmitOperand(EAX, dst);
280 CHECK(imm.is_int8());
281 EmitUint8(imm.value() & 0xFF);
282}
283
284
Ian Rogers2c8f6532011-09-02 17:16:34 -0700285void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700286 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
287 EmitUint8(0x0F);
288 EmitUint8(0xB7);
289 EmitRegisterOperand(dst, src);
290}
291
292
Ian Rogers2c8f6532011-09-02 17:16:34 -0700293void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700294 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
295 EmitUint8(0x0F);
296 EmitUint8(0xB7);
297 EmitOperand(dst, src);
298}
299
300
Ian Rogers2c8f6532011-09-02 17:16:34 -0700301void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700302 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
303 EmitUint8(0x0F);
304 EmitUint8(0xBF);
305 EmitRegisterOperand(dst, src);
306}
307
308
Ian Rogers2c8f6532011-09-02 17:16:34 -0700309void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700310 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
311 EmitUint8(0x0F);
312 EmitUint8(0xBF);
313 EmitOperand(dst, src);
314}
315
316
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700317void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700318 LOG(FATAL) << "Use movzxw or movsxw instead.";
319}
320
321
Ian Rogers2c8f6532011-09-02 17:16:34 -0700322void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700323 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
324 EmitOperandSizeOverride();
325 EmitUint8(0x89);
326 EmitOperand(src, dst);
327}
328
329
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100330void X86Assembler::movw(const Address& dst, const Immediate& imm) {
331 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
332 EmitOperandSizeOverride();
333 EmitUint8(0xC7);
334 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100335 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100336 EmitUint8(imm.value() & 0xFF);
337 EmitUint8(imm.value() >> 8);
338}
339
340
Ian Rogers2c8f6532011-09-02 17:16:34 -0700341void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
343 EmitUint8(0x8D);
344 EmitOperand(dst, src);
345}
346
347
Ian Rogers2c8f6532011-09-02 17:16:34 -0700348void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700349 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
350 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700351 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700352 EmitRegisterOperand(dst, src);
353}
354
355
Mark Mendellabdac472016-02-12 13:49:03 -0500356void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
357 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
358 EmitUint8(0x0F);
359 EmitUint8(0x40 + condition);
360 EmitOperand(dst, src);
361}
362
363
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000364void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700365 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
366 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700367 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000368 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700369}
370
371
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100372void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
373 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
374 EmitUint8(0x0F);
375 EmitUint8(0x28);
376 EmitXmmRegisterOperand(dst, src);
377}
378
379
Aart Bikc7782262017-01-13 16:20:08 -0800380void X86Assembler::movaps(XmmRegister dst, const Address& src) {
381 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
382 EmitUint8(0x0F);
383 EmitUint8(0x28);
384 EmitOperand(dst, src);
385}
386
387
388void X86Assembler::movups(XmmRegister dst, const Address& src) {
389 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
390 EmitUint8(0x0F);
391 EmitUint8(0x10);
392 EmitOperand(dst, src);
393}
394
395
396void X86Assembler::movaps(const Address& dst, XmmRegister src) {
397 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
398 EmitUint8(0x0F);
399 EmitUint8(0x29);
400 EmitOperand(src, dst);
401}
402
403
404void X86Assembler::movups(const Address& dst, XmmRegister src) {
405 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0xF3);
415 EmitUint8(0x0F);
416 EmitUint8(0x10);
417 EmitOperand(dst, src);
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0xF3);
424 EmitUint8(0x0F);
425 EmitUint8(0x11);
426 EmitOperand(src, dst);
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x11);
435 EmitXmmRegisterOperand(src, dst);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0x66);
442 EmitUint8(0x0F);
443 EmitUint8(0x6E);
444 EmitOperand(dst, Operand(src));
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0x66);
451 EmitUint8(0x0F);
452 EmitUint8(0x7E);
453 EmitOperand(src, Operand(dst));
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x58);
462 EmitXmmRegisterOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x58);
471 EmitOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x5C);
480 EmitXmmRegisterOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5C);
489 EmitOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x59);
498 EmitXmmRegisterOperand(dst, src);
499}
500
501
Ian Rogers2c8f6532011-09-02 17:16:34 -0700502void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0xF3);
505 EmitUint8(0x0F);
506 EmitUint8(0x59);
507 EmitOperand(dst, src);
508}
509
510
Ian Rogers2c8f6532011-09-02 17:16:34 -0700511void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700512 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
513 EmitUint8(0xF3);
514 EmitUint8(0x0F);
515 EmitUint8(0x5E);
516 EmitXmmRegisterOperand(dst, src);
517}
518
519
Ian Rogers2c8f6532011-09-02 17:16:34 -0700520void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700521 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
522 EmitUint8(0xF3);
523 EmitUint8(0x0F);
524 EmitUint8(0x5E);
525 EmitOperand(dst, src);
526}
527
528
Aart Bikc7782262017-01-13 16:20:08 -0800529void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
530 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
531 EmitUint8(0x0F);
532 EmitUint8(0x58);
533 EmitXmmRegisterOperand(dst, src);
534}
535
536
537void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
538 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
539 EmitUint8(0x0F);
540 EmitUint8(0x5C);
541 EmitXmmRegisterOperand(dst, src);
542}
543
544
545void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
546 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
547 EmitUint8(0x0F);
548 EmitUint8(0x59);
549 EmitXmmRegisterOperand(dst, src);
550}
551
552
553void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
554 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
555 EmitUint8(0x0F);
556 EmitUint8(0x5E);
557 EmitXmmRegisterOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x28);
566 EmitXmmRegisterOperand(dst, src);
567}
568
569
570void X86Assembler::movapd(XmmRegister dst, const Address& src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x28);
575 EmitOperand(dst, src);
576}
577
578
579void X86Assembler::movupd(XmmRegister dst, const Address& src) {
580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0x66);
582 EmitUint8(0x0F);
583 EmitUint8(0x10);
584 EmitOperand(dst, src);
585}
586
587
588void X86Assembler::movapd(const Address& dst, XmmRegister src) {
589 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
590 EmitUint8(0x66);
591 EmitUint8(0x0F);
592 EmitUint8(0x29);
593 EmitOperand(src, dst);
594}
595
596
597void X86Assembler::movupd(const Address& dst, XmmRegister src) {
598 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
599 EmitUint8(0x66);
600 EmitUint8(0x0F);
601 EmitUint8(0x11);
602 EmitOperand(src, dst);
603}
604
605
Ian Rogers2c8f6532011-09-02 17:16:34 -0700606void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700607 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
608 EmitUint8(0xD9);
609 EmitOperand(0, src);
610}
611
612
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500613void X86Assembler::fsts(const Address& dst) {
614 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
615 EmitUint8(0xD9);
616 EmitOperand(2, dst);
617}
618
619
Ian Rogers2c8f6532011-09-02 17:16:34 -0700620void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700621 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
622 EmitUint8(0xD9);
623 EmitOperand(3, dst);
624}
625
626
Ian Rogers2c8f6532011-09-02 17:16:34 -0700627void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0xF2);
630 EmitUint8(0x0F);
631 EmitUint8(0x10);
632 EmitOperand(dst, src);
633}
634
635
Ian Rogers2c8f6532011-09-02 17:16:34 -0700636void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0xF2);
639 EmitUint8(0x0F);
640 EmitUint8(0x11);
641 EmitOperand(src, dst);
642}
643
644
Ian Rogers2c8f6532011-09-02 17:16:34 -0700645void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF2);
648 EmitUint8(0x0F);
649 EmitUint8(0x11);
650 EmitXmmRegisterOperand(src, dst);
651}
652
653
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000654void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0x66);
657 EmitUint8(0x0F);
658 EmitUint8(0x16);
659 EmitOperand(dst, src);
660}
661
662
663void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0x66);
666 EmitUint8(0x0F);
667 EmitUint8(0x17);
668 EmitOperand(src, dst);
669}
670
671
Ian Rogers2c8f6532011-09-02 17:16:34 -0700672void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF2);
675 EmitUint8(0x0F);
676 EmitUint8(0x58);
677 EmitXmmRegisterOperand(dst, src);
678}
679
680
Ian Rogers2c8f6532011-09-02 17:16:34 -0700681void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF2);
684 EmitUint8(0x0F);
685 EmitUint8(0x58);
686 EmitOperand(dst, src);
687}
688
689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF2);
693 EmitUint8(0x0F);
694 EmitUint8(0x5C);
695 EmitXmmRegisterOperand(dst, src);
696}
697
698
Ian Rogers2c8f6532011-09-02 17:16:34 -0700699void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0xF2);
702 EmitUint8(0x0F);
703 EmitUint8(0x5C);
704 EmitOperand(dst, src);
705}
706
707
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
710 EmitUint8(0xF2);
711 EmitUint8(0x0F);
712 EmitUint8(0x59);
713 EmitXmmRegisterOperand(dst, src);
714}
715
716
Ian Rogers2c8f6532011-09-02 17:16:34 -0700717void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
719 EmitUint8(0xF2);
720 EmitUint8(0x0F);
721 EmitUint8(0x59);
722 EmitOperand(dst, src);
723}
724
725
Ian Rogers2c8f6532011-09-02 17:16:34 -0700726void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
728 EmitUint8(0xF2);
729 EmitUint8(0x0F);
730 EmitUint8(0x5E);
731 EmitXmmRegisterOperand(dst, src);
732}
733
734
Ian Rogers2c8f6532011-09-02 17:16:34 -0700735void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
737 EmitUint8(0xF2);
738 EmitUint8(0x0F);
739 EmitUint8(0x5E);
740 EmitOperand(dst, src);
741}
742
743
Aart Bikc7782262017-01-13 16:20:08 -0800744void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
745 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
746 EmitUint8(0x66);
747 EmitUint8(0x0F);
748 EmitUint8(0x58);
749 EmitXmmRegisterOperand(dst, src);
750}
751
752
753void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
755 EmitUint8(0x66);
756 EmitUint8(0x0F);
757 EmitUint8(0x5C);
758 EmitXmmRegisterOperand(dst, src);
759}
760
761
762void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
764 EmitUint8(0x66);
765 EmitUint8(0x0F);
766 EmitUint8(0x59);
767 EmitXmmRegisterOperand(dst, src);
768}
769
770
771void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
773 EmitUint8(0x66);
774 EmitUint8(0x0F);
775 EmitUint8(0x5E);
776 EmitXmmRegisterOperand(dst, src);
777}
778
779
Aart Bik68555e92017-02-13 14:28:45 -0800780void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
781 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
782 EmitUint8(0x66);
783 EmitUint8(0x0F);
784 EmitUint8(0x6F);
785 EmitXmmRegisterOperand(dst, src);
786}
787
788
789void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
791 EmitUint8(0x66);
792 EmitUint8(0x0F);
793 EmitUint8(0x6F);
794 EmitOperand(dst, src);
795}
796
797
798void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
799 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
800 EmitUint8(0xF3);
801 EmitUint8(0x0F);
802 EmitUint8(0x6F);
803 EmitOperand(dst, src);
804}
805
806
807void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
809 EmitUint8(0x66);
810 EmitUint8(0x0F);
811 EmitUint8(0x7F);
812 EmitOperand(src, dst);
813}
814
815
816void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
817 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
818 EmitUint8(0xF3);
819 EmitUint8(0x0F);
820 EmitUint8(0x7F);
821 EmitOperand(src, dst);
822}
823
824
Aart Bike69d7a92017-02-17 11:48:23 -0800825void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
826 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827 EmitUint8(0x66);
828 EmitUint8(0x0F);
829 EmitUint8(0xFC);
830 EmitXmmRegisterOperand(dst, src);
831}
832
833
834void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
836 EmitUint8(0x66);
837 EmitUint8(0x0F);
838 EmitUint8(0xF8);
839 EmitXmmRegisterOperand(dst, src);
840}
841
842
843void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
845 EmitUint8(0x66);
846 EmitUint8(0x0F);
847 EmitUint8(0xFD);
848 EmitXmmRegisterOperand(dst, src);
849}
850
851
852void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
854 EmitUint8(0x66);
855 EmitUint8(0x0F);
856 EmitUint8(0xF9);
857 EmitXmmRegisterOperand(dst, src);
858}
859
860
861void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0xD5);
866 EmitXmmRegisterOperand(dst, src);
867}
868
869
Aart Bik68555e92017-02-13 14:28:45 -0800870void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
871 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
872 EmitUint8(0x66);
873 EmitUint8(0x0F);
874 EmitUint8(0xFE);
875 EmitXmmRegisterOperand(dst, src);
876}
877
878
879void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
880 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
881 EmitUint8(0x66);
882 EmitUint8(0x0F);
883 EmitUint8(0xFA);
884 EmitXmmRegisterOperand(dst, src);
885}
886
887
888void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
889 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
890 EmitUint8(0x66);
891 EmitUint8(0x0F);
892 EmitUint8(0x38);
893 EmitUint8(0x40);
894 EmitXmmRegisterOperand(dst, src);
895}
896
897
Aart Bike69d7a92017-02-17 11:48:23 -0800898void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0x66);
901 EmitUint8(0x0F);
902 EmitUint8(0xD4);
903 EmitXmmRegisterOperand(dst, src);
904}
905
906
907void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
909 EmitUint8(0x66);
910 EmitUint8(0x0F);
911 EmitUint8(0xFB);
912 EmitXmmRegisterOperand(dst, src);
913}
914
915
Aart Bik4ca17352018-03-07 15:47:39 -0800916void X86Assembler::paddusb(XmmRegister dst, XmmRegister src) {
917 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
918 EmitUint8(0x66);
919 EmitUint8(0x0F);
920 EmitUint8(0xDC);
921 EmitXmmRegisterOperand(dst, src);
922}
923
924
925void X86Assembler::paddsb(XmmRegister dst, XmmRegister src) {
926 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
927 EmitUint8(0x66);
928 EmitUint8(0x0F);
929 EmitUint8(0xEC);
930 EmitXmmRegisterOperand(dst, src);
931}
932
933
934void X86Assembler::paddusw(XmmRegister dst, XmmRegister src) {
935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
936 EmitUint8(0x66);
937 EmitUint8(0x0F);
938 EmitUint8(0xDD);
939 EmitXmmRegisterOperand(dst, src);
940}
941
942
943void X86Assembler::paddsw(XmmRegister dst, XmmRegister src) {
944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
945 EmitUint8(0x66);
946 EmitUint8(0x0F);
947 EmitUint8(0xED);
948 EmitXmmRegisterOperand(dst, src);
949}
950
951
952void X86Assembler::psubusb(XmmRegister dst, XmmRegister src) {
953 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954 EmitUint8(0x66);
955 EmitUint8(0x0F);
956 EmitUint8(0xD8);
957 EmitXmmRegisterOperand(dst, src);
958}
959
960
961void X86Assembler::psubsb(XmmRegister dst, XmmRegister src) {
962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0x66);
964 EmitUint8(0x0F);
965 EmitUint8(0xE8);
966 EmitXmmRegisterOperand(dst, src);
967}
968
969
970void X86Assembler::psubusw(XmmRegister dst, XmmRegister src) {
971 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
972 EmitUint8(0x66);
973 EmitUint8(0x0F);
974 EmitUint8(0xD9);
975 EmitXmmRegisterOperand(dst, src);
976}
977
978
979void X86Assembler::psubsw(XmmRegister dst, XmmRegister src) {
980 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
981 EmitUint8(0x66);
982 EmitUint8(0x0F);
983 EmitUint8(0xE9);
984 EmitXmmRegisterOperand(dst, src);
985}
986
987
Ian Rogers2c8f6532011-09-02 17:16:34 -0700988void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700989 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
990 EmitUint8(0xF3);
991 EmitUint8(0x0F);
992 EmitUint8(0x2A);
993 EmitOperand(dst, Operand(src));
994}
995
996
Ian Rogers2c8f6532011-09-02 17:16:34 -0700997void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700998 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
999 EmitUint8(0xF2);
1000 EmitUint8(0x0F);
1001 EmitUint8(0x2A);
1002 EmitOperand(dst, Operand(src));
1003}
1004
1005
Ian Rogers2c8f6532011-09-02 17:16:34 -07001006void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001007 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1008 EmitUint8(0xF3);
1009 EmitUint8(0x0F);
1010 EmitUint8(0x2D);
1011 EmitXmmRegisterOperand(dst, src);
1012}
1013
1014
Ian Rogers2c8f6532011-09-02 17:16:34 -07001015void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001016 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1017 EmitUint8(0xF3);
1018 EmitUint8(0x0F);
1019 EmitUint8(0x5A);
1020 EmitXmmRegisterOperand(dst, src);
1021}
1022
1023
Ian Rogers2c8f6532011-09-02 17:16:34 -07001024void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001025 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1026 EmitUint8(0xF2);
1027 EmitUint8(0x0F);
1028 EmitUint8(0x2D);
1029 EmitXmmRegisterOperand(dst, src);
1030}
1031
1032
Ian Rogers2c8f6532011-09-02 17:16:34 -07001033void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001034 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1035 EmitUint8(0xF3);
1036 EmitUint8(0x0F);
1037 EmitUint8(0x2C);
1038 EmitXmmRegisterOperand(dst, src);
1039}
1040
1041
Ian Rogers2c8f6532011-09-02 17:16:34 -07001042void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1044 EmitUint8(0xF2);
1045 EmitUint8(0x0F);
1046 EmitUint8(0x2C);
1047 EmitXmmRegisterOperand(dst, src);
1048}
1049
1050
Ian Rogers2c8f6532011-09-02 17:16:34 -07001051void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001052 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1053 EmitUint8(0xF2);
1054 EmitUint8(0x0F);
1055 EmitUint8(0x5A);
1056 EmitXmmRegisterOperand(dst, src);
1057}
1058
1059
Aart Bik3ae3b592017-02-24 14:09:15 -08001060void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
1061 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1062 EmitUint8(0x0F);
1063 EmitUint8(0x5B);
1064 EmitXmmRegisterOperand(dst, src);
1065}
1066
1067
Ian Rogers2c8f6532011-09-02 17:16:34 -07001068void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1070 EmitUint8(0xF3);
1071 EmitUint8(0x0F);
1072 EmitUint8(0xE6);
1073 EmitXmmRegisterOperand(dst, src);
1074}
1075
1076
Ian Rogers2c8f6532011-09-02 17:16:34 -07001077void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001078 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1079 EmitUint8(0x0F);
1080 EmitUint8(0x2F);
1081 EmitXmmRegisterOperand(a, b);
1082}
1083
1084
Aart Bik18ba1212016-08-01 14:11:20 -07001085void X86Assembler::comiss(XmmRegister a, const Address& b) {
1086 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1087 EmitUint8(0x0F);
1088 EmitUint8(0x2F);
1089 EmitOperand(a, b);
1090}
1091
1092
Ian Rogers2c8f6532011-09-02 17:16:34 -07001093void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1095 EmitUint8(0x66);
1096 EmitUint8(0x0F);
1097 EmitUint8(0x2F);
1098 EmitXmmRegisterOperand(a, b);
1099}
1100
1101
Aart Bik18ba1212016-08-01 14:11:20 -07001102void X86Assembler::comisd(XmmRegister a, const Address& b) {
1103 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1104 EmitUint8(0x66);
1105 EmitUint8(0x0F);
1106 EmitUint8(0x2F);
1107 EmitOperand(a, b);
1108}
1109
1110
Calin Juravleddb7df22014-11-25 20:56:51 +00001111void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1112 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1113 EmitUint8(0x0F);
1114 EmitUint8(0x2E);
1115 EmitXmmRegisterOperand(a, b);
1116}
1117
1118
Mark Mendell9f51f262015-10-30 09:21:37 -04001119void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1120 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1121 EmitUint8(0x0F);
1122 EmitUint8(0x2E);
1123 EmitOperand(a, b);
1124}
1125
1126
Calin Juravleddb7df22014-11-25 20:56:51 +00001127void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1129 EmitUint8(0x66);
1130 EmitUint8(0x0F);
1131 EmitUint8(0x2E);
1132 EmitXmmRegisterOperand(a, b);
1133}
1134
1135
Mark Mendell9f51f262015-10-30 09:21:37 -04001136void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1137 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1138 EmitUint8(0x66);
1139 EmitUint8(0x0F);
1140 EmitUint8(0x2E);
1141 EmitOperand(a, b);
1142}
1143
1144
Mark Mendellfb8d2792015-03-31 22:16:59 -04001145void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1146 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1147 EmitUint8(0x66);
1148 EmitUint8(0x0F);
1149 EmitUint8(0x3A);
1150 EmitUint8(0x0B);
1151 EmitXmmRegisterOperand(dst, src);
1152 EmitUint8(imm.value());
1153}
1154
1155
1156void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1157 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1158 EmitUint8(0x66);
1159 EmitUint8(0x0F);
1160 EmitUint8(0x3A);
1161 EmitUint8(0x0A);
1162 EmitXmmRegisterOperand(dst, src);
1163 EmitUint8(imm.value());
1164}
1165
1166
Ian Rogers2c8f6532011-09-02 17:16:34 -07001167void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001168 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1169 EmitUint8(0xF2);
1170 EmitUint8(0x0F);
1171 EmitUint8(0x51);
1172 EmitXmmRegisterOperand(dst, src);
1173}
1174
1175
Ian Rogers2c8f6532011-09-02 17:16:34 -07001176void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001177 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1178 EmitUint8(0xF3);
1179 EmitUint8(0x0F);
1180 EmitUint8(0x51);
1181 EmitXmmRegisterOperand(dst, src);
1182}
1183
1184
Ian Rogers2c8f6532011-09-02 17:16:34 -07001185void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001186 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1187 EmitUint8(0x66);
1188 EmitUint8(0x0F);
1189 EmitUint8(0x57);
1190 EmitOperand(dst, src);
1191}
1192
1193
Ian Rogers2c8f6532011-09-02 17:16:34 -07001194void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001195 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1196 EmitUint8(0x66);
1197 EmitUint8(0x0F);
1198 EmitUint8(0x57);
1199 EmitXmmRegisterOperand(dst, src);
1200}
1201
1202
Aart Bik68555e92017-02-13 14:28:45 -08001203void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001204 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1205 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001206 EmitUint8(0x57);
1207 EmitOperand(dst, src);
1208}
1209
1210
1211void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1212 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1213 EmitUint8(0x0F);
1214 EmitUint8(0x57);
1215 EmitXmmRegisterOperand(dst, src);
1216}
1217
1218
1219void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1220 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1221 EmitUint8(0x66);
1222 EmitUint8(0x0F);
1223 EmitUint8(0xEF);
Mark Mendell09ed1a32015-03-25 08:30:06 -04001224 EmitXmmRegisterOperand(dst, src);
1225}
1226
1227
1228void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1229 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1230 EmitUint8(0x66);
1231 EmitUint8(0x0F);
1232 EmitUint8(0x54);
1233 EmitXmmRegisterOperand(dst, src);
1234}
1235
1236
Aart Bik68555e92017-02-13 14:28:45 -08001237void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001238 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1239 EmitUint8(0x66);
1240 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001241 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001242 EmitOperand(dst, src);
1243}
1244
1245
Aart Bik68555e92017-02-13 14:28:45 -08001246void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
Mark Mendell09ed1a32015-03-25 08:30:06 -04001247 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1248 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001249 EmitUint8(0x54);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001250 EmitXmmRegisterOperand(dst, src);
1251}
1252
1253
Mark Mendell09ed1a32015-03-25 08:30:06 -04001254void X86Assembler::andps(XmmRegister dst, const Address& src) {
1255 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1256 EmitUint8(0x0F);
1257 EmitUint8(0x54);
1258 EmitOperand(dst, src);
1259}
1260
1261
Aart Bik68555e92017-02-13 14:28:45 -08001262void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001263 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1264 EmitUint8(0x66);
1265 EmitUint8(0x0F);
Aart Bik68555e92017-02-13 14:28:45 -08001266 EmitUint8(0xDB);
1267 EmitXmmRegisterOperand(dst, src);
1268}
1269
1270
Aart Bik21c580b2017-03-13 11:52:07 -07001271void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
1272 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1273 EmitUint8(0x66);
1274 EmitUint8(0x0F);
1275 EmitUint8(0x55);
1276 EmitXmmRegisterOperand(dst, src);
1277}
1278
1279
1280void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
1281 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1282 EmitUint8(0x0F);
1283 EmitUint8(0x55);
1284 EmitXmmRegisterOperand(dst, src);
1285}
1286
1287
1288void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
1289 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1290 EmitUint8(0x66);
1291 EmitUint8(0x0F);
1292 EmitUint8(0xDF);
1293 EmitXmmRegisterOperand(dst, src);
1294}
1295
1296
Aart Bik68555e92017-02-13 14:28:45 -08001297void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1298 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1299 EmitUint8(0x66);
1300 EmitUint8(0x0F);
1301 EmitUint8(0x56);
1302 EmitXmmRegisterOperand(dst, src);
1303}
1304
1305
1306void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1307 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1308 EmitUint8(0x0F);
1309 EmitUint8(0x56);
1310 EmitXmmRegisterOperand(dst, src);
1311}
1312
1313
1314void X86Assembler::por(XmmRegister dst, XmmRegister src) {
1315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1316 EmitUint8(0x66);
1317 EmitUint8(0x0F);
1318 EmitUint8(0xEB);
1319 EmitXmmRegisterOperand(dst, src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001320}
1321
1322
Aart Bik67d3fd72017-03-31 15:11:53 -07001323void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
1324 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1325 EmitUint8(0x66);
1326 EmitUint8(0x0F);
1327 EmitUint8(0xE0);
1328 EmitXmmRegisterOperand(dst, src);
1329}
1330
1331
1332void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
1333 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1334 EmitUint8(0x66);
1335 EmitUint8(0x0F);
1336 EmitUint8(0xE3);
1337 EmitXmmRegisterOperand(dst, src);
1338}
1339
Aart Bik6005a872017-07-24 13:33:39 -07001340
1341void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
1342 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1343 EmitUint8(0x66);
1344 EmitUint8(0x0F);
1345 EmitUint8(0xF6);
1346 EmitXmmRegisterOperand(dst, src);
1347}
1348
1349
1350void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
1351 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1352 EmitUint8(0x66);
1353 EmitUint8(0x0F);
1354 EmitUint8(0xF5);
1355 EmitXmmRegisterOperand(dst, src);
1356}
1357
1358
1359void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
1360 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1361 EmitUint8(0x66);
1362 EmitUint8(0x0F);
1363 EmitUint8(0x38);
1364 EmitUint8(0x01);
1365 EmitXmmRegisterOperand(dst, src);
1366}
1367
1368
1369void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
1370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1371 EmitUint8(0x66);
1372 EmitUint8(0x0F);
1373 EmitUint8(0x38);
1374 EmitUint8(0x02);
1375 EmitXmmRegisterOperand(dst, src);
1376}
1377
1378
1379void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
1380 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1381 EmitUint8(0xF2);
1382 EmitUint8(0x0F);
1383 EmitUint8(0x7C);
1384 EmitXmmRegisterOperand(dst, src);
1385}
1386
1387
1388void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
1389 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1390 EmitUint8(0x66);
1391 EmitUint8(0x0F);
1392 EmitUint8(0x7C);
1393 EmitXmmRegisterOperand(dst, src);
1394}
1395
1396
1397void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
1398 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1399 EmitUint8(0x66);
1400 EmitUint8(0x0F);
1401 EmitUint8(0x38);
1402 EmitUint8(0x05);
1403 EmitXmmRegisterOperand(dst, src);
1404}
1405
1406
1407void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
1408 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1409 EmitUint8(0x66);
1410 EmitUint8(0x0F);
1411 EmitUint8(0x38);
1412 EmitUint8(0x06);
1413 EmitXmmRegisterOperand(dst, src);
1414}
1415
1416
1417void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
1418 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1419 EmitUint8(0xF2);
1420 EmitUint8(0x0F);
1421 EmitUint8(0x7D);
1422 EmitXmmRegisterOperand(dst, src);
1423}
1424
1425
1426void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
1427 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1428 EmitUint8(0x66);
1429 EmitUint8(0x0F);
1430 EmitUint8(0x7D);
1431 EmitXmmRegisterOperand(dst, src);
1432}
1433
1434
Aart Bikc8e93c72017-05-10 10:49:22 -07001435void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
1436 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1437 EmitUint8(0x66);
1438 EmitUint8(0x0F);
1439 EmitUint8(0x38);
1440 EmitUint8(0x38);
1441 EmitXmmRegisterOperand(dst, src);
1442}
1443
1444void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
1445 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1446 EmitUint8(0x66);
1447 EmitUint8(0x0F);
1448 EmitUint8(0x38);
1449 EmitUint8(0x3C);
1450 EmitXmmRegisterOperand(dst, src);
1451}
1452
1453void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
1454 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1455 EmitUint8(0x66);
1456 EmitUint8(0x0F);
1457 EmitUint8(0xEA);
1458 EmitXmmRegisterOperand(dst, src);
1459}
1460
1461void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
1462 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1463 EmitUint8(0x66);
1464 EmitUint8(0x0F);
1465 EmitUint8(0xEE);
1466 EmitXmmRegisterOperand(dst, src);
1467}
1468
1469void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
1470 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1471 EmitUint8(0x66);
1472 EmitUint8(0x0F);
1473 EmitUint8(0x38);
1474 EmitUint8(0x39);
1475 EmitXmmRegisterOperand(dst, src);
1476}
1477
1478void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
1479 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1480 EmitUint8(0x66);
1481 EmitUint8(0x0F);
1482 EmitUint8(0x38);
1483 EmitUint8(0x3D);
1484 EmitXmmRegisterOperand(dst, src);
1485}
1486
1487void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
1488 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1489 EmitUint8(0x66);
1490 EmitUint8(0x0F);
1491 EmitUint8(0xDA);
1492 EmitXmmRegisterOperand(dst, src);
1493}
1494
1495void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
1496 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1497 EmitUint8(0x66);
1498 EmitUint8(0x0F);
1499 EmitUint8(0xDE);
1500 EmitXmmRegisterOperand(dst, src);
1501}
1502
1503void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
1504 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1505 EmitUint8(0x66);
1506 EmitUint8(0x0F);
1507 EmitUint8(0x38);
1508 EmitUint8(0x3A);
1509 EmitXmmRegisterOperand(dst, src);
1510}
1511
1512void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
1513 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1514 EmitUint8(0x66);
1515 EmitUint8(0x0F);
1516 EmitUint8(0x38);
1517 EmitUint8(0x3E);
1518 EmitXmmRegisterOperand(dst, src);
1519}
1520
1521void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
1522 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1523 EmitUint8(0x66);
1524 EmitUint8(0x0F);
1525 EmitUint8(0x38);
1526 EmitUint8(0x3B);
1527 EmitXmmRegisterOperand(dst, src);
1528}
1529
1530void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
1531 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1532 EmitUint8(0x66);
1533 EmitUint8(0x0F);
1534 EmitUint8(0x38);
1535 EmitUint8(0x3F);
1536 EmitXmmRegisterOperand(dst, src);
1537}
1538
1539void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
1540 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1541 EmitUint8(0x0F);
1542 EmitUint8(0x5D);
1543 EmitXmmRegisterOperand(dst, src);
1544}
1545
1546void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
1547 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1548 EmitUint8(0x0F);
1549 EmitUint8(0x5F);
1550 EmitXmmRegisterOperand(dst, src);
1551}
1552
1553void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
1554 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1555 EmitUint8(0x66);
1556 EmitUint8(0x0F);
1557 EmitUint8(0x5D);
1558 EmitXmmRegisterOperand(dst, src);
1559}
1560
1561void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
1562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1563 EmitUint8(0x66);
1564 EmitUint8(0x0F);
1565 EmitUint8(0x5F);
1566 EmitXmmRegisterOperand(dst, src);
1567}
Aart Bik67d3fd72017-03-31 15:11:53 -07001568
Aart Bik4b455332017-03-15 11:19:35 -07001569void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
1570 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1571 EmitUint8(0x66);
1572 EmitUint8(0x0F);
1573 EmitUint8(0x74);
1574 EmitXmmRegisterOperand(dst, src);
1575}
1576
1577
1578void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
1579 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1580 EmitUint8(0x66);
1581 EmitUint8(0x0F);
1582 EmitUint8(0x75);
1583 EmitXmmRegisterOperand(dst, src);
1584}
1585
1586
1587void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
1588 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1589 EmitUint8(0x66);
1590 EmitUint8(0x0F);
1591 EmitUint8(0x76);
1592 EmitXmmRegisterOperand(dst, src);
1593}
1594
1595
1596void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
1597 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1598 EmitUint8(0x66);
1599 EmitUint8(0x0F);
1600 EmitUint8(0x38);
1601 EmitUint8(0x29);
1602 EmitXmmRegisterOperand(dst, src);
1603}
1604
1605
Aart Bik8939c642017-04-03 14:09:01 -07001606void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
1607 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1608 EmitUint8(0x66);
1609 EmitUint8(0x0F);
1610 EmitUint8(0x64);
1611 EmitXmmRegisterOperand(dst, src);
1612}
1613
1614
1615void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
1616 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1617 EmitUint8(0x66);
1618 EmitUint8(0x0F);
1619 EmitUint8(0x65);
1620 EmitXmmRegisterOperand(dst, src);
1621}
1622
1623
1624void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
1625 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1626 EmitUint8(0x66);
1627 EmitUint8(0x0F);
1628 EmitUint8(0x66);
1629 EmitXmmRegisterOperand(dst, src);
1630}
1631
1632
1633void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
1634 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1635 EmitUint8(0x66);
1636 EmitUint8(0x0F);
1637 EmitUint8(0x38);
1638 EmitUint8(0x37);
1639 EmitXmmRegisterOperand(dst, src);
1640}
1641
1642
Aart Bik12e06ed2017-01-31 16:11:24 -08001643void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1644 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1645 EmitUint8(0x66);
1646 EmitUint8(0x0F);
1647 EmitUint8(0xC6);
1648 EmitXmmRegisterOperand(dst, src);
1649 EmitUint8(imm.value());
1650}
1651
1652
1653void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1654 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1655 EmitUint8(0x0F);
1656 EmitUint8(0xC6);
1657 EmitXmmRegisterOperand(dst, src);
1658 EmitUint8(imm.value());
1659}
1660
1661
Aart Bik68555e92017-02-13 14:28:45 -08001662void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1663 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1664 EmitUint8(0x66);
1665 EmitUint8(0x0F);
1666 EmitUint8(0x70);
1667 EmitXmmRegisterOperand(dst, src);
1668 EmitUint8(imm.value());
1669}
1670
1671
Aart Bike69d7a92017-02-17 11:48:23 -08001672void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
1673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1674 EmitUint8(0x66);
1675 EmitUint8(0x0F);
1676 EmitUint8(0x60);
1677 EmitXmmRegisterOperand(dst, src);
1678}
1679
1680
1681void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
1682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1683 EmitUint8(0x66);
1684 EmitUint8(0x0F);
1685 EmitUint8(0x61);
1686 EmitXmmRegisterOperand(dst, src);
1687}
1688
1689
1690void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
1691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1692 EmitUint8(0x66);
1693 EmitUint8(0x0F);
1694 EmitUint8(0x62);
1695 EmitXmmRegisterOperand(dst, src);
1696}
1697
1698
1699void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
1700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1701 EmitUint8(0x66);
1702 EmitUint8(0x0F);
1703 EmitUint8(0x6C);
1704 EmitXmmRegisterOperand(dst, src);
1705}
1706
1707
Aart Bik3332db82017-08-11 15:10:30 -07001708void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
1709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1710 EmitUint8(0x66);
1711 EmitUint8(0x0F);
1712 EmitUint8(0x68);
1713 EmitXmmRegisterOperand(dst, src);
1714}
1715
1716
1717void X86Assembler::punpckhwd(XmmRegister dst, XmmRegister src) {
1718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1719 EmitUint8(0x66);
1720 EmitUint8(0x0F);
1721 EmitUint8(0x69);
1722 EmitXmmRegisterOperand(dst, src);
1723}
1724
1725
1726void X86Assembler::punpckhdq(XmmRegister dst, XmmRegister src) {
1727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1728 EmitUint8(0x66);
1729 EmitUint8(0x0F);
1730 EmitUint8(0x6A);
1731 EmitXmmRegisterOperand(dst, src);
1732}
1733
1734
1735void X86Assembler::punpckhqdq(XmmRegister dst, XmmRegister src) {
1736 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1737 EmitUint8(0x66);
1738 EmitUint8(0x0F);
1739 EmitUint8(0x6D);
1740 EmitXmmRegisterOperand(dst, src);
1741}
1742
1743
Aart Bike69d7a92017-02-17 11:48:23 -08001744void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
1745 DCHECK(shift_count.is_uint8());
1746 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1747 EmitUint8(0x66);
1748 EmitUint8(0x0F);
1749 EmitUint8(0x71);
1750 EmitXmmRegisterOperand(6, reg);
1751 EmitUint8(shift_count.value());
1752}
1753
1754
1755void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
1756 DCHECK(shift_count.is_uint8());
1757 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1758 EmitUint8(0x66);
1759 EmitUint8(0x0F);
1760 EmitUint8(0x72);
1761 EmitXmmRegisterOperand(6, reg);
1762 EmitUint8(shift_count.value());
1763}
1764
1765
1766void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
1767 DCHECK(shift_count.is_uint8());
1768 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1769 EmitUint8(0x66);
1770 EmitUint8(0x0F);
1771 EmitUint8(0x73);
1772 EmitXmmRegisterOperand(6, reg);
1773 EmitUint8(shift_count.value());
1774}
1775
1776
1777void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
1778 DCHECK(shift_count.is_uint8());
1779 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1780 EmitUint8(0x66);
1781 EmitUint8(0x0F);
1782 EmitUint8(0x71);
1783 EmitXmmRegisterOperand(4, reg);
1784 EmitUint8(shift_count.value());
1785}
1786
1787
1788void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
1789 DCHECK(shift_count.is_uint8());
1790 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1791 EmitUint8(0x66);
1792 EmitUint8(0x0F);
1793 EmitUint8(0x72);
1794 EmitXmmRegisterOperand(4, reg);
1795 EmitUint8(shift_count.value());
1796}
1797
1798
1799void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
1800 DCHECK(shift_count.is_uint8());
1801 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1802 EmitUint8(0x66);
1803 EmitUint8(0x0F);
1804 EmitUint8(0x71);
1805 EmitXmmRegisterOperand(2, reg);
1806 EmitUint8(shift_count.value());
1807}
1808
1809
1810void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
1811 DCHECK(shift_count.is_uint8());
1812 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1813 EmitUint8(0x66);
1814 EmitUint8(0x0F);
1815 EmitUint8(0x72);
1816 EmitXmmRegisterOperand(2, reg);
1817 EmitUint8(shift_count.value());
1818}
1819
1820
1821void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
1822 DCHECK(shift_count.is_uint8());
1823 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1824 EmitUint8(0x66);
1825 EmitUint8(0x0F);
1826 EmitUint8(0x73);
1827 EmitXmmRegisterOperand(2, reg);
1828 EmitUint8(shift_count.value());
1829}
1830
1831
1832void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
1833 DCHECK(shift_count.is_uint8());
1834 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1835 EmitUint8(0x66);
1836 EmitUint8(0x0F);
1837 EmitUint8(0x73);
1838 EmitXmmRegisterOperand(3, reg);
1839 EmitUint8(shift_count.value());
1840}
1841
1842
Ian Rogers2c8f6532011-09-02 17:16:34 -07001843void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1845 EmitUint8(0xDD);
1846 EmitOperand(0, src);
1847}
1848
1849
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001850void X86Assembler::fstl(const Address& dst) {
1851 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1852 EmitUint8(0xDD);
1853 EmitOperand(2, dst);
1854}
1855
1856
Ian Rogers2c8f6532011-09-02 17:16:34 -07001857void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001858 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1859 EmitUint8(0xDD);
1860 EmitOperand(3, dst);
1861}
1862
1863
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001864void X86Assembler::fstsw() {
1865 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1866 EmitUint8(0x9B);
1867 EmitUint8(0xDF);
1868 EmitUint8(0xE0);
1869}
1870
1871
Ian Rogers2c8f6532011-09-02 17:16:34 -07001872void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001873 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1874 EmitUint8(0xD9);
1875 EmitOperand(7, dst);
1876}
1877
1878
Ian Rogers2c8f6532011-09-02 17:16:34 -07001879void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001880 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1881 EmitUint8(0xD9);
1882 EmitOperand(5, src);
1883}
1884
1885
Ian Rogers2c8f6532011-09-02 17:16:34 -07001886void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001887 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1888 EmitUint8(0xDF);
1889 EmitOperand(7, dst);
1890}
1891
1892
Ian Rogers2c8f6532011-09-02 17:16:34 -07001893void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001894 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1895 EmitUint8(0xDB);
1896 EmitOperand(3, dst);
1897}
1898
1899
Ian Rogers2c8f6532011-09-02 17:16:34 -07001900void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001901 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1902 EmitUint8(0xDF);
1903 EmitOperand(5, src);
1904}
1905
1906
Roland Levillain0a186012015-04-13 17:00:20 +01001907void X86Assembler::filds(const Address& src) {
1908 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1909 EmitUint8(0xDB);
1910 EmitOperand(0, src);
1911}
1912
1913
Ian Rogers2c8f6532011-09-02 17:16:34 -07001914void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001915 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1916 EmitUint8(0xD9);
1917 EmitUint8(0xF7);
1918}
1919
1920
Ian Rogers2c8f6532011-09-02 17:16:34 -07001921void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001922 CHECK_LT(index.value(), 7);
1923 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1924 EmitUint8(0xDD);
1925 EmitUint8(0xC0 + index.value());
1926}
1927
1928
Ian Rogers2c8f6532011-09-02 17:16:34 -07001929void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001930 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1931 EmitUint8(0xD9);
1932 EmitUint8(0xFE);
1933}
1934
1935
Ian Rogers2c8f6532011-09-02 17:16:34 -07001936void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001937 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1938 EmitUint8(0xD9);
1939 EmitUint8(0xFF);
1940}
1941
1942
Ian Rogers2c8f6532011-09-02 17:16:34 -07001943void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001944 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1945 EmitUint8(0xD9);
1946 EmitUint8(0xF2);
1947}
1948
1949
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001950void X86Assembler::fucompp() {
1951 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1952 EmitUint8(0xDA);
1953 EmitUint8(0xE9);
1954}
1955
1956
1957void X86Assembler::fprem() {
1958 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1959 EmitUint8(0xD9);
1960 EmitUint8(0xF8);
1961}
1962
1963
Ian Rogers2c8f6532011-09-02 17:16:34 -07001964void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001965 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1966 EmitUint8(0x87);
1967 EmitRegisterOperand(dst, src);
1968}
1969
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001970
Ian Rogers7caad772012-03-30 01:07:54 -07001971void X86Assembler::xchgl(Register reg, const Address& address) {
1972 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1973 EmitUint8(0x87);
1974 EmitOperand(reg, address);
1975}
1976
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001977
Serguei Katkov3b625932016-05-06 10:24:17 +06001978void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1979 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1980 EmitUint8(0x80);
1981 EmitOperand(7, address);
1982 EmitUint8(imm.value() & 0xFF);
1983}
1984
1985
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001986void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1988 EmitUint8(0x66);
Vladimir Marko29a8d842018-02-13 13:46:15 +00001989 EmitComplex(7, address, imm, /* is_16_op */ true);
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001990}
1991
1992
Ian Rogers2c8f6532011-09-02 17:16:34 -07001993void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001994 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1995 EmitComplex(7, Operand(reg), imm);
1996}
1997
1998
Ian Rogers2c8f6532011-09-02 17:16:34 -07001999void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002000 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2001 EmitUint8(0x3B);
2002 EmitOperand(reg0, Operand(reg1));
2003}
2004
2005
Ian Rogers2c8f6532011-09-02 17:16:34 -07002006void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002007 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2008 EmitUint8(0x3B);
2009 EmitOperand(reg, address);
2010}
2011
2012
Ian Rogers2c8f6532011-09-02 17:16:34 -07002013void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002014 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2015 EmitUint8(0x03);
2016 EmitRegisterOperand(dst, src);
2017}
2018
2019
Ian Rogers2c8f6532011-09-02 17:16:34 -07002020void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2022 EmitUint8(0x03);
2023 EmitOperand(reg, address);
2024}
2025
2026
Ian Rogers2c8f6532011-09-02 17:16:34 -07002027void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002028 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2029 EmitUint8(0x39);
2030 EmitOperand(reg, address);
2031}
2032
2033
Ian Rogers2c8f6532011-09-02 17:16:34 -07002034void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002035 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2036 EmitComplex(7, address, imm);
2037}
2038
2039
Ian Rogers2c8f6532011-09-02 17:16:34 -07002040void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002041 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2042 EmitUint8(0x85);
2043 EmitRegisterOperand(reg1, reg2);
2044}
2045
2046
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01002047void X86Assembler::testl(Register reg, const Address& address) {
2048 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2049 EmitUint8(0x85);
2050 EmitOperand(reg, address);
2051}
2052
2053
Ian Rogers2c8f6532011-09-02 17:16:34 -07002054void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002055 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2056 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
2057 // we only test the byte register to keep the encoding short.
2058 if (immediate.is_uint8() && reg < 4) {
2059 // Use zero-extended 8-bit immediate.
2060 if (reg == EAX) {
2061 EmitUint8(0xA8);
2062 } else {
2063 EmitUint8(0xF6);
2064 EmitUint8(0xC0 + reg);
2065 }
2066 EmitUint8(immediate.value() & 0xFF);
2067 } else if (reg == EAX) {
2068 // Use short form if the destination is EAX.
2069 EmitUint8(0xA9);
2070 EmitImmediate(immediate);
2071 } else {
2072 EmitUint8(0xF7);
2073 EmitOperand(0, Operand(reg));
2074 EmitImmediate(immediate);
2075 }
2076}
2077
2078
Vladimir Marko953437b2016-08-24 08:30:46 +00002079void X86Assembler::testb(const Address& dst, const Immediate& imm) {
2080 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2081 EmitUint8(0xF6);
2082 EmitOperand(EAX, dst);
2083 CHECK(imm.is_int8());
2084 EmitUint8(imm.value() & 0xFF);
2085}
2086
2087
2088void X86Assembler::testl(const Address& dst, const Immediate& imm) {
2089 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2090 EmitUint8(0xF7);
2091 EmitOperand(0, dst);
2092 EmitImmediate(imm);
2093}
2094
2095
Ian Rogers2c8f6532011-09-02 17:16:34 -07002096void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002097 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2098 EmitUint8(0x23);
2099 EmitOperand(dst, Operand(src));
2100}
2101
2102
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002103void X86Assembler::andl(Register reg, const Address& address) {
2104 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2105 EmitUint8(0x23);
2106 EmitOperand(reg, address);
2107}
2108
2109
Ian Rogers2c8f6532011-09-02 17:16:34 -07002110void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002111 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2112 EmitComplex(4, Operand(dst), imm);
2113}
2114
2115
Ian Rogers2c8f6532011-09-02 17:16:34 -07002116void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002117 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2118 EmitUint8(0x0B);
2119 EmitOperand(dst, Operand(src));
2120}
2121
2122
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002123void X86Assembler::orl(Register reg, const Address& address) {
2124 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2125 EmitUint8(0x0B);
2126 EmitOperand(reg, address);
2127}
2128
2129
Ian Rogers2c8f6532011-09-02 17:16:34 -07002130void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002131 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2132 EmitComplex(1, Operand(dst), imm);
2133}
2134
2135
Ian Rogers2c8f6532011-09-02 17:16:34 -07002136void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002137 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2138 EmitUint8(0x33);
2139 EmitOperand(dst, Operand(src));
2140}
2141
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002142
2143void X86Assembler::xorl(Register reg, const Address& address) {
2144 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2145 EmitUint8(0x33);
2146 EmitOperand(reg, address);
2147}
2148
2149
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01002150void X86Assembler::xorl(Register dst, const Immediate& imm) {
2151 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2152 EmitComplex(6, Operand(dst), imm);
2153}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002154
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00002155
Ian Rogers2c8f6532011-09-02 17:16:34 -07002156void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002157 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2158 EmitComplex(0, Operand(reg), imm);
2159}
2160
2161
Ian Rogers2c8f6532011-09-02 17:16:34 -07002162void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002163 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2164 EmitUint8(0x01);
2165 EmitOperand(reg, address);
2166}
2167
2168
Ian Rogers2c8f6532011-09-02 17:16:34 -07002169void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002170 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2171 EmitComplex(0, address, imm);
2172}
2173
2174
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002175void X86Assembler::addw(const Address& address, const Immediate& imm) {
2176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2177 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
2178 EmitUint8(0x66);
2179 EmitComplex(0, address, imm, /* is_16_op */ true);
2180}
2181
2182
Ian Rogers2c8f6532011-09-02 17:16:34 -07002183void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002184 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2185 EmitComplex(2, Operand(reg), imm);
2186}
2187
2188
Ian Rogers2c8f6532011-09-02 17:16:34 -07002189void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2191 EmitUint8(0x13);
2192 EmitOperand(dst, Operand(src));
2193}
2194
2195
Ian Rogers2c8f6532011-09-02 17:16:34 -07002196void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002197 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2198 EmitUint8(0x13);
2199 EmitOperand(dst, address);
2200}
2201
2202
Ian Rogers2c8f6532011-09-02 17:16:34 -07002203void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002204 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2205 EmitUint8(0x2B);
2206 EmitOperand(dst, Operand(src));
2207}
2208
2209
Ian Rogers2c8f6532011-09-02 17:16:34 -07002210void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002211 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2212 EmitComplex(5, Operand(reg), imm);
2213}
2214
2215
Ian Rogers2c8f6532011-09-02 17:16:34 -07002216void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2218 EmitUint8(0x2B);
2219 EmitOperand(reg, address);
2220}
2221
2222
Mark Mendell09ed1a32015-03-25 08:30:06 -04002223void X86Assembler::subl(const Address& address, Register reg) {
2224 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2225 EmitUint8(0x29);
2226 EmitOperand(reg, address);
2227}
2228
2229
Ian Rogers2c8f6532011-09-02 17:16:34 -07002230void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002231 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2232 EmitUint8(0x99);
2233}
2234
2235
Ian Rogers2c8f6532011-09-02 17:16:34 -07002236void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002237 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2238 EmitUint8(0xF7);
2239 EmitUint8(0xF8 | reg);
2240}
2241
2242
Ian Rogers2c8f6532011-09-02 17:16:34 -07002243void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002244 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2245 EmitUint8(0x0F);
2246 EmitUint8(0xAF);
2247 EmitOperand(dst, Operand(src));
2248}
2249
2250
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002251void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04002253 // See whether imm can be represented as a sign-extended 8bit value.
2254 int32_t v32 = static_cast<int32_t>(imm.value());
2255 if (IsInt<8>(v32)) {
2256 // Sign-extension works.
2257 EmitUint8(0x6B);
2258 EmitOperand(dst, Operand(src));
2259 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
2260 } else {
2261 // Not representable, use full immediate.
2262 EmitUint8(0x69);
2263 EmitOperand(dst, Operand(src));
2264 EmitImmediate(imm);
2265 }
2266}
2267
2268
2269void X86Assembler::imull(Register reg, const Immediate& imm) {
2270 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002271}
2272
2273
Ian Rogers2c8f6532011-09-02 17:16:34 -07002274void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2276 EmitUint8(0x0F);
2277 EmitUint8(0xAF);
2278 EmitOperand(reg, address);
2279}
2280
2281
Ian Rogers2c8f6532011-09-02 17:16:34 -07002282void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2284 EmitUint8(0xF7);
2285 EmitOperand(5, Operand(reg));
2286}
2287
2288
Ian Rogers2c8f6532011-09-02 17:16:34 -07002289void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002290 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2291 EmitUint8(0xF7);
2292 EmitOperand(5, address);
2293}
2294
2295
Ian Rogers2c8f6532011-09-02 17:16:34 -07002296void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002297 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2298 EmitUint8(0xF7);
2299 EmitOperand(4, Operand(reg));
2300}
2301
2302
Ian Rogers2c8f6532011-09-02 17:16:34 -07002303void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2305 EmitUint8(0xF7);
2306 EmitOperand(4, address);
2307}
2308
2309
Ian Rogers2c8f6532011-09-02 17:16:34 -07002310void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002311 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2312 EmitUint8(0x1B);
2313 EmitOperand(dst, Operand(src));
2314}
2315
2316
Ian Rogers2c8f6532011-09-02 17:16:34 -07002317void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002318 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2319 EmitComplex(3, Operand(reg), imm);
2320}
2321
2322
Ian Rogers2c8f6532011-09-02 17:16:34 -07002323void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002324 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2325 EmitUint8(0x1B);
2326 EmitOperand(dst, address);
2327}
2328
2329
Mark Mendell09ed1a32015-03-25 08:30:06 -04002330void X86Assembler::sbbl(const Address& address, Register src) {
2331 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2332 EmitUint8(0x19);
2333 EmitOperand(src, address);
2334}
2335
2336
Ian Rogers2c8f6532011-09-02 17:16:34 -07002337void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2339 EmitUint8(0x40 + reg);
2340}
2341
2342
Ian Rogers2c8f6532011-09-02 17:16:34 -07002343void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002344 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2345 EmitUint8(0xFF);
2346 EmitOperand(0, address);
2347}
2348
2349
Ian Rogers2c8f6532011-09-02 17:16:34 -07002350void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002351 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2352 EmitUint8(0x48 + reg);
2353}
2354
2355
Ian Rogers2c8f6532011-09-02 17:16:34 -07002356void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002357 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2358 EmitUint8(0xFF);
2359 EmitOperand(1, address);
2360}
2361
2362
Ian Rogers2c8f6532011-09-02 17:16:34 -07002363void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002364 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002365}
2366
2367
Ian Rogers2c8f6532011-09-02 17:16:34 -07002368void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002369 EmitGenericShift(4, Operand(operand), shifter);
2370}
2371
2372
2373void X86Assembler::shll(const Address& address, const Immediate& imm) {
2374 EmitGenericShift(4, address, imm);
2375}
2376
2377
2378void X86Assembler::shll(const Address& address, Register shifter) {
2379 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002380}
2381
2382
Ian Rogers2c8f6532011-09-02 17:16:34 -07002383void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002384 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002385}
2386
2387
Ian Rogers2c8f6532011-09-02 17:16:34 -07002388void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002389 EmitGenericShift(5, Operand(operand), shifter);
2390}
2391
2392
2393void X86Assembler::shrl(const Address& address, const Immediate& imm) {
2394 EmitGenericShift(5, address, imm);
2395}
2396
2397
2398void X86Assembler::shrl(const Address& address, Register shifter) {
2399 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002400}
2401
2402
Ian Rogers2c8f6532011-09-02 17:16:34 -07002403void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00002404 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002405}
2406
2407
Ian Rogers2c8f6532011-09-02 17:16:34 -07002408void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00002409 EmitGenericShift(7, Operand(operand), shifter);
2410}
2411
2412
2413void X86Assembler::sarl(const Address& address, const Immediate& imm) {
2414 EmitGenericShift(7, address, imm);
2415}
2416
2417
2418void X86Assembler::sarl(const Address& address, Register shifter) {
2419 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002420}
2421
2422
Calin Juravle9aec02f2014-11-18 23:06:35 +00002423void X86Assembler::shld(Register dst, Register src, Register shifter) {
2424 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002425 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2426 EmitUint8(0x0F);
2427 EmitUint8(0xA5);
2428 EmitRegisterOperand(src, dst);
2429}
2430
2431
Mark P Mendell73945692015-04-29 14:56:17 +00002432void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
2433 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2434 EmitUint8(0x0F);
2435 EmitUint8(0xA4);
2436 EmitRegisterOperand(src, dst);
2437 EmitUint8(imm.value() & 0xFF);
2438}
2439
2440
Calin Juravle9aec02f2014-11-18 23:06:35 +00002441void X86Assembler::shrd(Register dst, Register src, Register shifter) {
2442 DCHECK_EQ(ECX, shifter);
2443 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2444 EmitUint8(0x0F);
2445 EmitUint8(0xAD);
2446 EmitRegisterOperand(src, dst);
2447}
2448
2449
Mark P Mendell73945692015-04-29 14:56:17 +00002450void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
2451 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2452 EmitUint8(0x0F);
2453 EmitUint8(0xAC);
2454 EmitRegisterOperand(src, dst);
2455 EmitUint8(imm.value() & 0xFF);
2456}
2457
2458
Mark Mendellbcee0922015-09-15 21:45:01 -04002459void X86Assembler::roll(Register reg, const Immediate& imm) {
2460 EmitGenericShift(0, Operand(reg), imm);
2461}
2462
2463
2464void X86Assembler::roll(Register operand, Register shifter) {
2465 EmitGenericShift(0, Operand(operand), shifter);
2466}
2467
2468
2469void X86Assembler::rorl(Register reg, const Immediate& imm) {
2470 EmitGenericShift(1, Operand(reg), imm);
2471}
2472
2473
2474void X86Assembler::rorl(Register operand, Register shifter) {
2475 EmitGenericShift(1, Operand(operand), shifter);
2476}
2477
2478
Ian Rogers2c8f6532011-09-02 17:16:34 -07002479void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002480 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2481 EmitUint8(0xF7);
2482 EmitOperand(3, Operand(reg));
2483}
2484
2485
Ian Rogers2c8f6532011-09-02 17:16:34 -07002486void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002487 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2488 EmitUint8(0xF7);
2489 EmitUint8(0xD0 | reg);
2490}
2491
2492
Ian Rogers2c8f6532011-09-02 17:16:34 -07002493void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2495 EmitUint8(0xC8);
2496 CHECK(imm.is_uint16());
2497 EmitUint8(imm.value() & 0xFF);
2498 EmitUint8((imm.value() >> 8) & 0xFF);
2499 EmitUint8(0x00);
2500}
2501
2502
Ian Rogers2c8f6532011-09-02 17:16:34 -07002503void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002504 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2505 EmitUint8(0xC9);
2506}
2507
2508
Ian Rogers2c8f6532011-09-02 17:16:34 -07002509void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002510 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2511 EmitUint8(0xC3);
2512}
2513
2514
Ian Rogers2c8f6532011-09-02 17:16:34 -07002515void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002516 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2517 EmitUint8(0xC2);
2518 CHECK(imm.is_uint16());
2519 EmitUint8(imm.value() & 0xFF);
2520 EmitUint8((imm.value() >> 8) & 0xFF);
2521}
2522
2523
2524
Ian Rogers2c8f6532011-09-02 17:16:34 -07002525void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002526 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2527 EmitUint8(0x90);
2528}
2529
2530
Ian Rogers2c8f6532011-09-02 17:16:34 -07002531void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002532 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2533 EmitUint8(0xCC);
2534}
2535
2536
Ian Rogers2c8f6532011-09-02 17:16:34 -07002537void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002538 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2539 EmitUint8(0xF4);
2540}
2541
2542
Ian Rogers2c8f6532011-09-02 17:16:34 -07002543void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2545 if (label->IsBound()) {
2546 static const int kShortSize = 2;
2547 static const int kLongSize = 6;
2548 int offset = label->Position() - buffer_.Size();
2549 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002550 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002551 EmitUint8(0x70 + condition);
2552 EmitUint8((offset - kShortSize) & 0xFF);
2553 } else {
2554 EmitUint8(0x0F);
2555 EmitUint8(0x80 + condition);
2556 EmitInt32(offset - kLongSize);
2557 }
2558 } else {
2559 EmitUint8(0x0F);
2560 EmitUint8(0x80 + condition);
2561 EmitLabelLink(label);
2562 }
2563}
2564
2565
Mark Mendell73f455e2015-08-21 09:30:05 -04002566void X86Assembler::j(Condition condition, NearLabel* label) {
2567 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2568 if (label->IsBound()) {
2569 static const int kShortSize = 2;
2570 int offset = label->Position() - buffer_.Size();
2571 CHECK_LE(offset, 0);
2572 CHECK(IsInt<8>(offset - kShortSize));
2573 EmitUint8(0x70 + condition);
2574 EmitUint8((offset - kShortSize) & 0xFF);
2575 } else {
2576 EmitUint8(0x70 + condition);
2577 EmitLabelLink(label);
2578 }
2579}
2580
2581
2582void X86Assembler::jecxz(NearLabel* label) {
2583 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2584 if (label->IsBound()) {
2585 static const int kShortSize = 2;
2586 int offset = label->Position() - buffer_.Size();
2587 CHECK_LE(offset, 0);
2588 CHECK(IsInt<8>(offset - kShortSize));
2589 EmitUint8(0xE3);
2590 EmitUint8((offset - kShortSize) & 0xFF);
2591 } else {
2592 EmitUint8(0xE3);
2593 EmitLabelLink(label);
2594 }
2595}
2596
2597
Ian Rogers2c8f6532011-09-02 17:16:34 -07002598void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002599 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2600 EmitUint8(0xFF);
2601 EmitRegisterOperand(4, reg);
2602}
2603
Ian Rogers7caad772012-03-30 01:07:54 -07002604void X86Assembler::jmp(const Address& address) {
2605 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2606 EmitUint8(0xFF);
2607 EmitOperand(4, address);
2608}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002609
Ian Rogers2c8f6532011-09-02 17:16:34 -07002610void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002611 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2612 if (label->IsBound()) {
2613 static const int kShortSize = 2;
2614 static const int kLongSize = 5;
2615 int offset = label->Position() - buffer_.Size();
2616 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08002617 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002618 EmitUint8(0xEB);
2619 EmitUint8((offset - kShortSize) & 0xFF);
2620 } else {
2621 EmitUint8(0xE9);
2622 EmitInt32(offset - kLongSize);
2623 }
2624 } else {
2625 EmitUint8(0xE9);
2626 EmitLabelLink(label);
2627 }
2628}
2629
2630
Mark Mendell73f455e2015-08-21 09:30:05 -04002631void X86Assembler::jmp(NearLabel* label) {
2632 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2633 if (label->IsBound()) {
2634 static const int kShortSize = 2;
2635 int offset = label->Position() - buffer_.Size();
2636 CHECK_LE(offset, 0);
2637 CHECK(IsInt<8>(offset - kShortSize));
2638 EmitUint8(0xEB);
2639 EmitUint8((offset - kShortSize) & 0xFF);
2640 } else {
2641 EmitUint8(0xEB);
2642 EmitLabelLink(label);
2643 }
2644}
2645
2646
jessicahandojob03d6402016-09-07 12:16:53 -07002647void X86Assembler::repne_scasb() {
2648 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2649 EmitUint8(0xF2);
2650 EmitUint8(0xAE);
2651}
2652
2653
Andreas Gampe21030dd2015-05-07 14:46:15 -07002654void X86Assembler::repne_scasw() {
2655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2656 EmitUint8(0x66);
2657 EmitUint8(0xF2);
2658 EmitUint8(0xAF);
2659}
2660
2661
jessicahandojob03d6402016-09-07 12:16:53 -07002662void X86Assembler::repe_cmpsb() {
2663 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2664 EmitUint8(0xF2);
2665 EmitUint8(0xA6);
2666}
2667
2668
agicsaki71311f82015-07-27 11:34:13 -07002669void X86Assembler::repe_cmpsw() {
2670 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2671 EmitUint8(0x66);
2672 EmitUint8(0xF3);
2673 EmitUint8(0xA7);
2674}
2675
2676
agicsaki970abfb2015-07-31 10:31:14 -07002677void X86Assembler::repe_cmpsl() {
2678 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2679 EmitUint8(0xF3);
2680 EmitUint8(0xA7);
2681}
2682
2683
jessicahandojob03d6402016-09-07 12:16:53 -07002684void X86Assembler::rep_movsb() {
2685 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2686 EmitUint8(0xF3);
2687 EmitUint8(0xA4);
2688}
2689
2690
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04002691void X86Assembler::rep_movsw() {
2692 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2693 EmitUint8(0x66);
2694 EmitUint8(0xF3);
2695 EmitUint8(0xA5);
2696}
2697
2698
Ian Rogers2c8f6532011-09-02 17:16:34 -07002699X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2701 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07002702 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002703}
2704
2705
Ian Rogers2c8f6532011-09-02 17:16:34 -07002706void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002707 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2708 EmitUint8(0x0F);
2709 EmitUint8(0xB1);
2710 EmitOperand(reg, address);
2711}
2712
Mark Mendell58d25fd2015-04-03 14:52:31 -04002713
2714void X86Assembler::cmpxchg8b(const Address& address) {
2715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2716 EmitUint8(0x0F);
2717 EmitUint8(0xC7);
2718 EmitOperand(1, address);
2719}
2720
2721
Elliott Hughes79ab9e32012-03-12 15:41:35 -07002722void X86Assembler::mfence() {
2723 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2724 EmitUint8(0x0F);
2725 EmitUint8(0xAE);
2726 EmitUint8(0xF0);
2727}
2728
Ian Rogers2c8f6532011-09-02 17:16:34 -07002729X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07002730 // TODO: fs is a prefix and not an instruction
2731 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2732 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07002733 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07002734}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002735
Ian Rogersbefbd572014-03-06 01:13:39 -08002736X86Assembler* X86Assembler::gs() {
2737 // TODO: fs is a prefix and not an instruction
2738 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2739 EmitUint8(0x65);
2740 return this;
2741}
2742
Ian Rogers2c8f6532011-09-02 17:16:34 -07002743void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002744 int value = imm.value();
2745 if (value > 0) {
2746 if (value == 1) {
2747 incl(reg);
2748 } else if (value != 0) {
2749 addl(reg, imm);
2750 }
2751 } else if (value < 0) {
2752 value = -value;
2753 if (value == 1) {
2754 decl(reg);
2755 } else if (value != 0) {
2756 subl(reg, Immediate(value));
2757 }
2758 }
2759}
2760
2761
Roland Levillain647b9ed2014-11-27 12:06:00 +00002762void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
2763 // TODO: Need to have a code constants table.
2764 pushl(Immediate(High32Bits(value)));
2765 pushl(Immediate(Low32Bits(value)));
2766 movsd(dst, Address(ESP, 0));
2767 addl(ESP, Immediate(2 * sizeof(int32_t)));
2768}
2769
2770
Ian Rogers2c8f6532011-09-02 17:16:34 -07002771void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002772 // TODO: Need to have a code constants table.
2773 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002774 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002775}
2776
2777
Ian Rogers2c8f6532011-09-02 17:16:34 -07002778void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002779 CHECK(IsPowerOfTwo(alignment));
2780 // Emit nop instruction until the real position is aligned.
2781 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2782 nop();
2783 }
2784}
2785
2786
Ian Rogers2c8f6532011-09-02 17:16:34 -07002787void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002788 int bound = buffer_.Size();
2789 CHECK(!label->IsBound()); // Labels can only be bound once.
2790 while (label->IsLinked()) {
2791 int position = label->LinkPosition();
2792 int next = buffer_.Load<int32_t>(position);
2793 buffer_.Store<int32_t>(position, bound - (position + 4));
2794 label->position_ = next;
2795 }
2796 label->BindTo(bound);
2797}
2798
2799
Mark Mendell73f455e2015-08-21 09:30:05 -04002800void X86Assembler::Bind(NearLabel* label) {
2801 int bound = buffer_.Size();
2802 CHECK(!label->IsBound()); // Labels can only be bound once.
2803 while (label->IsLinked()) {
2804 int position = label->LinkPosition();
2805 uint8_t delta = buffer_.Load<uint8_t>(position);
2806 int offset = bound - (position + 1);
2807 CHECK(IsInt<8>(offset));
2808 buffer_.Store<int8_t>(position, offset);
2809 label->position_ = delta != 0u ? label->position_ - delta : 0;
2810 }
2811 label->BindTo(bound);
2812}
2813
2814
Ian Rogers44fb0d02012-03-23 16:46:24 -07002815void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2816 CHECK_GE(reg_or_opcode, 0);
2817 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002818 const int length = operand.length_;
2819 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002820 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002821 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002822 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002823 // Emit the rest of the encoded operand.
2824 for (int i = 1; i < length; i++) {
2825 EmitUint8(operand.encoding_[i]);
2826 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002827 AssemblerFixup* fixup = operand.GetFixup();
2828 if (fixup != nullptr) {
2829 EmitFixup(fixup);
2830 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002831}
2832
2833
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002834void X86Assembler::EmitImmediate(const Immediate& imm, bool is_16_op) {
2835 if (is_16_op) {
2836 EmitUint8(imm.value() & 0xFF);
2837 EmitUint8(imm.value() >> 8);
2838 } else {
2839 EmitInt32(imm.value());
2840 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002841}
2842
2843
Ian Rogers44fb0d02012-03-23 16:46:24 -07002844void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002845 const Operand& operand,
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002846 const Immediate& immediate,
2847 bool is_16_op) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002848 CHECK_GE(reg_or_opcode, 0);
2849 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002850 if (immediate.is_int8()) {
2851 // Use sign-extended 8-bit immediate.
2852 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002853 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002854 EmitUint8(immediate.value() & 0xFF);
2855 } else if (operand.IsRegister(EAX)) {
2856 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002857 EmitUint8(0x05 + (reg_or_opcode << 3));
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002858 EmitImmediate(immediate, is_16_op);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002859 } else {
2860 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002861 EmitOperand(reg_or_opcode, operand);
Nicolas Geoffrayded55942018-01-26 16:33:41 +00002862 EmitImmediate(immediate, is_16_op);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002863 }
2864}
2865
2866
Ian Rogers2c8f6532011-09-02 17:16:34 -07002867void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002868 if (label->IsBound()) {
2869 int offset = label->Position() - buffer_.Size();
2870 CHECK_LE(offset, 0);
2871 EmitInt32(offset - instruction_size);
2872 } else {
2873 EmitLabelLink(label);
2874 }
2875}
2876
2877
Ian Rogers2c8f6532011-09-02 17:16:34 -07002878void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002879 CHECK(!label->IsBound());
2880 int position = buffer_.Size();
2881 EmitInt32(label->position_);
2882 label->LinkTo(position);
2883}
2884
2885
Mark Mendell73f455e2015-08-21 09:30:05 -04002886void X86Assembler::EmitLabelLink(NearLabel* label) {
2887 CHECK(!label->IsBound());
2888 int position = buffer_.Size();
2889 if (label->IsLinked()) {
2890 // Save the delta in the byte that we have to play with.
2891 uint32_t delta = position - label->LinkPosition();
2892 CHECK(IsUint<8>(delta));
2893 EmitUint8(delta & 0xFF);
2894 } else {
2895 EmitUint8(0);
2896 }
2897 label->LinkTo(position);
2898}
2899
2900
Ian Rogers44fb0d02012-03-23 16:46:24 -07002901void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002902 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002903 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002904 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2905 CHECK(imm.is_int8());
2906 if (imm.value() == 1) {
2907 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002908 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002909 } else {
2910 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002911 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002912 EmitUint8(imm.value() & 0xFF);
2913 }
2914}
2915
2916
Ian Rogers44fb0d02012-03-23 16:46:24 -07002917void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002918 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002919 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002920 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2921 CHECK_EQ(shifter, ECX);
2922 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002923 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002924}
2925
Mark Mendell0616ae02015-04-17 12:49:27 -04002926void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002927 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002928 // Generate the data for the literal area.
2929 for (size_t i = 0, e = area.size(); i < e; i++) {
2930 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2931 EmitInt32(area[i]);
2932 }
2933}
2934
Mark Mendell805b3b52015-09-18 14:10:29 -04002935size_t ConstantArea::AppendInt32(int32_t v) {
2936 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002937 buffer_.push_back(v);
2938 return result;
2939}
2940
Mark Mendell805b3b52015-09-18 14:10:29 -04002941size_t ConstantArea::AddInt32(int32_t v) {
2942 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2943 if (v == buffer_[i]) {
2944 return i * elem_size_;
2945 }
2946 }
2947
2948 // Didn't match anything.
2949 return AppendInt32(v);
2950}
2951
2952size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002953 int32_t v_low = Low32Bits(v);
2954 int32_t v_high = High32Bits(v);
2955 if (buffer_.size() > 1) {
2956 // Ensure we don't pass the end of the buffer.
2957 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2958 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002959 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002960 }
2961 }
2962 }
2963
2964 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002965 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002966 buffer_.push_back(v_low);
2967 buffer_.push_back(v_high);
2968 return result;
2969}
2970
Mark Mendell805b3b52015-09-18 14:10:29 -04002971size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002972 // Treat the value as a 64-bit integer value.
2973 return AddInt64(bit_cast<int64_t, double>(v));
2974}
2975
Mark Mendell805b3b52015-09-18 14:10:29 -04002976size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002977 // Treat the value as a 32-bit integer value.
2978 return AddInt32(bit_cast<int32_t, float>(v));
2979}
2980
Ian Rogers2c8f6532011-09-02 17:16:34 -07002981} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002982} // namespace art